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EVEX_INSTRUCTIONS()::
# EMITTING VADDNEPBF16 (VADDNEPBF16-128-1)
{
ICLASS:      VADDNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x58 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VADDNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x58 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VADDNEPBF16 (VADDNEPBF16-256-1)
{
ICLASS:      VADDNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x58 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VADDNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x58 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VADDNEPBF16 (VADDNEPBF16-512-1)
{
ICLASS:      VADDNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x58 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VADDNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x58 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VCMPPBF16 (VCMPPBF16-128-1)
{
ICLASS:      VCMPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xC2 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16 IMM0:r:b
IFORM:       VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512
}

{
ICLASS:      VCMPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xC2 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512
}


# EMITTING VCMPPBF16 (VCMPPBF16-256-1)
{
ICLASS:      VCMPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xC2 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16 IMM0:r:b
IFORM:       VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512
}

{
ICLASS:      VCMPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xC2 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512
}


# EMITTING VCMPPBF16 (VCMPPBF16-512-1)
{
ICLASS:      VCMPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xC2 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16 IMM0:r:b
IFORM:       VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512
}

{
ICLASS:      VCMPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xC2 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512
}


# EMITTING VCOMSBF16 (VCOMSBF16-128-1)
{
ICLASS:      VCOMSBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_SCALAR
EXCEPTIONS:  AVX512-E10NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  FLUSH_INPUT_DENORM SIMD_SCALAR 
PATTERN:     EVV 0x2F V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():r:dq:bf16 REG1=XMM_B3():r:dq:bf16
IFORM:       VCOMSBF16_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VCOMSBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_SCALAR
EXCEPTIONS:  AVX512-E10NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  DISP8_SCALAR FLUSH_INPUT_DENORM SIMD_SCALAR 
PATTERN:     EVV 0x2F V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 FIX_ROUND_LEN128() NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    REG0=XMM_R3():r:dq:bf16 MEM0:r:wrd:bf16
IFORM:       VCOMSBF16_XMMbf16_MEMbf16_AVX512
}


# EMITTING VDIVNEPBF16 (VDIVNEPBF16-128-1)
{
ICLASS:      VDIVNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VDIVNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VDIVNEPBF16 (VDIVNEPBF16-256-1)
{
ICLASS:      VDIVNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VDIVNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VDIVNEPBF16 (VDIVNEPBF16-512-1)
{
ICLASS:      VDIVNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VDIVNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD132NEPBF16 (VFMADD132NEPBF16-128-1)
{
ICLASS:      VFMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x98 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x98 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD132NEPBF16 (VFMADD132NEPBF16-256-1)
{
ICLASS:      VFMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x98 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x98 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD132NEPBF16 (VFMADD132NEPBF16-512-1)
{
ICLASS:      VFMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x98 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x98 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD213NEPBF16 (VFMADD213NEPBF16-128-1)
{
ICLASS:      VFMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xA8 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xA8 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD213NEPBF16 (VFMADD213NEPBF16-256-1)
{
ICLASS:      VFMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xA8 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xA8 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD213NEPBF16 (VFMADD213NEPBF16-512-1)
{
ICLASS:      VFMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xA8 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xA8 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD231NEPBF16 (VFMADD231NEPBF16-128-1)
{
ICLASS:      VFMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xB8 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xB8 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD231NEPBF16 (VFMADD231NEPBF16-256-1)
{
ICLASS:      VFMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xB8 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xB8 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFMADD231NEPBF16 (VFMADD231NEPBF16-512-1)
{
ICLASS:      VFMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xB8 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xB8 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB132NEPBF16 (VFMSUB132NEPBF16-128-1)
{
ICLASS:      VFMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9A VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9A VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB132NEPBF16 (VFMSUB132NEPBF16-256-1)
{
ICLASS:      VFMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9A VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9A VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB132NEPBF16 (VFMSUB132NEPBF16-512-1)
{
ICLASS:      VFMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9A VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9A VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB213NEPBF16 (VFMSUB213NEPBF16-128-1)
{
ICLASS:      VFMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAA VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAA VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB213NEPBF16 (VFMSUB213NEPBF16-256-1)
{
ICLASS:      VFMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAA VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAA VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB213NEPBF16 (VFMSUB213NEPBF16-512-1)
{
ICLASS:      VFMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAA VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAA VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB231NEPBF16 (VFMSUB231NEPBF16-128-1)
{
ICLASS:      VFMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBA VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBA VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB231NEPBF16 (VFMSUB231NEPBF16-256-1)
{
ICLASS:      VFMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBA VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBA VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFMSUB231NEPBF16 (VFMSUB231NEPBF16-512-1)
{
ICLASS:      VFMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBA VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBA VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD132NEPBF16 (VFNMADD132NEPBF16-128-1)
{
ICLASS:      VFNMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFNMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD132NEPBF16 (VFNMADD132NEPBF16-256-1)
{
ICLASS:      VFNMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFNMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD132NEPBF16 (VFNMADD132NEPBF16-512-1)
{
ICLASS:      VFNMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFNMADD132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD213NEPBF16 (VFNMADD213NEPBF16-128-1)
{
ICLASS:      VFNMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAC VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFNMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAC VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD213NEPBF16 (VFNMADD213NEPBF16-256-1)
{
ICLASS:      VFNMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAC VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFNMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAC VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD213NEPBF16 (VFNMADD213NEPBF16-512-1)
{
ICLASS:      VFNMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAC VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFNMADD213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAC VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD231NEPBF16 (VFNMADD231NEPBF16-128-1)
{
ICLASS:      VFNMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBC VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFNMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBC VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD231NEPBF16 (VFNMADD231NEPBF16-256-1)
{
ICLASS:      VFNMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBC VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFNMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBC VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMADD231NEPBF16 (VFNMADD231NEPBF16-512-1)
{
ICLASS:      VFNMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBC VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFNMADD231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBC VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB132NEPBF16 (VFNMSUB132NEPBF16-128-1)
{
ICLASS:      VFNMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9E VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFNMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9E VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB132NEPBF16 (VFNMSUB132NEPBF16-256-1)
{
ICLASS:      VFNMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9E VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFNMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9E VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB132NEPBF16 (VFNMSUB132NEPBF16-512-1)
{
ICLASS:      VFNMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x9E VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFNMSUB132NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x9E VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB213NEPBF16 (VFNMSUB213NEPBF16-128-1)
{
ICLASS:      VFNMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAE VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFNMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAE VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB213NEPBF16 (VFNMSUB213NEPBF16-256-1)
{
ICLASS:      VFNMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAE VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFNMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAE VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB213NEPBF16 (VFNMSUB213NEPBF16-512-1)
{
ICLASS:      VFNMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xAE VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFNMSUB213NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xAE VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB231NEPBF16 (VFNMSUB231NEPBF16-128-1)
{
ICLASS:      VFNMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBE VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VFNMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBE VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB231NEPBF16 (VFNMSUB231NEPBF16-256-1)
{
ICLASS:      VFNMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBE VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VFNMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBE VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VFNMSUB231NEPBF16 (VFNMSUB231NEPBF16-512-1)
{
ICLASS:      VFNMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0xBE VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VFNMSUB231NEPBF16
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xBE VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VFPCLASSPBF16 (VFPCLASSPBF16-128-1)
{
ICLASS:      VFPCLASSPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x66 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:bf16 IMM0:r:b
IFORM:       VFPCLASSPBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512
}

{
ICLASS:      VFPCLASSPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x66 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128
}


# EMITTING VFPCLASSPBF16 (VFPCLASSPBF16-256-1)
{
ICLASS:      VFPCLASSPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x66 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:bf16 IMM0:r:b
IFORM:       VFPCLASSPBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512
}

{
ICLASS:      VFPCLASSPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x66 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256
}


# EMITTING VFPCLASSPBF16 (VFPCLASSPBF16-512-1)
{
ICLASS:      VFPCLASSPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x66 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zbf16 IMM0:r:b
IFORM:       VFPCLASSPBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512
}

{
ICLASS:      VFPCLASSPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x66 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512
}


# EMITTING VGETEXPPBF16 (VGETEXPPBF16-128-1)
{
ICLASS:      VGETEXPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x42 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VGETEXPPBF16_XMMu16_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VGETEXPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x42 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VGETEXPPBF16_XMMu16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VGETEXPPBF16 (VGETEXPPBF16-256-1)
{
ICLASS:      VGETEXPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x42 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VGETEXPPBF16_YMMu16_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VGETEXPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x42 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VGETEXPPBF16_YMMu16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VGETEXPPBF16 (VGETEXPPBF16-512-1)
{
ICLASS:      VGETEXPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x42 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VGETEXPPBF16_ZMMu16_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VGETEXPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x42 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VGETEXPPBF16_ZMMu16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VGETMANTPBF16 (VGETMANTPBF16-128-1)
{
ICLASS:      VGETMANTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x26 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16 IMM0:r:b
IFORM:       VGETMANTPBF16_XMMu16_MASKmskw_XMMbf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x26 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPBF16_XMMu16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VGETMANTPBF16 (VGETMANTPBF16-256-1)
{
ICLASS:      VGETMANTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x26 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16 IMM0:r:b
IFORM:       VGETMANTPBF16_YMMu16_MASKmskw_YMMbf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x26 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPBF16_YMMu16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VGETMANTPBF16 (VGETMANTPBF16-512-1)
{
ICLASS:      VGETMANTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x26 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16 IMM0:r:b
IFORM:       VGETMANTPBF16_ZMMu16_MASKmskw_ZMMbf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x26 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPBF16_ZMMu16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VMAXPBF16 (VMAXPBF16-128-1)
{
ICLASS:      VMAXPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5F V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VMAXPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5F V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VMAXPBF16 (VMAXPBF16-256-1)
{
ICLASS:      VMAXPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5F V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VMAXPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5F V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VMAXPBF16 (VMAXPBF16-512-1)
{
ICLASS:      VMAXPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5F V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VMAXPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5F V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VMINPBF16 (VMINPBF16-128-1)
{
ICLASS:      VMINPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VMINPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VMINPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMINPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VMINPBF16 (VMINPBF16-256-1)
{
ICLASS:      VMINPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VMINPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VMINPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMINPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VMINPBF16 (VMINPBF16-512-1)
{
ICLASS:      VMINPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VMINPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VMULNEPBF16 (VMULNEPBF16-128-1)
{
ICLASS:      VMULNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x59 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VMULNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x59 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VMULNEPBF16 (VMULNEPBF16-256-1)
{
ICLASS:      VMULNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x59 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VMULNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x59 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VMULNEPBF16 (VMULNEPBF16-512-1)
{
ICLASS:      VMULNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x59 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VMULNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x59 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VRCPPBF16 (VRCPPBF16-128-1)
{
ICLASS:      VRCPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x4C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VRCPPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VRCPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x4C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VRCPPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VRCPPBF16 (VRCPPBF16-256-1)
{
ICLASS:      VRCPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x4C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VRCPPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VRCPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x4C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VRCPPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VRCPPBF16 (VRCPPBF16-512-1)
{
ICLASS:      VRCPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x4C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VRCPPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VRCPPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x4C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VRCPPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VREDUCENEPBF16 (VREDUCENEPBF16-128-1)
{
ICLASS:      VREDUCENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x56 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16 IMM0:r:b
IFORM:       VREDUCENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512
}

{
ICLASS:      VREDUCENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x56 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VREDUCENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VREDUCENEPBF16 (VREDUCENEPBF16-256-1)
{
ICLASS:      VREDUCENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x56 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16 IMM0:r:b
IFORM:       VREDUCENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512
}

{
ICLASS:      VREDUCENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x56 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VREDUCENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VREDUCENEPBF16 (VREDUCENEPBF16-512-1)
{
ICLASS:      VREDUCENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x56 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16 IMM0:r:b
IFORM:       VREDUCENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512
}

{
ICLASS:      VREDUCENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x56 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VREDUCENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VRNDSCALENEPBF16 (VRNDSCALENEPBF16-128-1)
{
ICLASS:      VRNDSCALENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x08 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16 IMM0:r:b
IFORM:       VRNDSCALENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x08 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VRNDSCALENEPBF16 (VRNDSCALENEPBF16-256-1)
{
ICLASS:      VRNDSCALENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x08 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16 IMM0:r:b
IFORM:       VRNDSCALENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x08 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VRNDSCALENEPBF16 (VRNDSCALENEPBF16-512-1)
{
ICLASS:      VRNDSCALENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x08 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16 IMM0:r:b
IFORM:       VRNDSCALENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALENEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x08 VF2 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
}


# EMITTING VRSQRTPBF16 (VRSQRTPBF16-128-1)
{
ICLASS:      VRSQRTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x4E VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VRSQRTPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VRSQRTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x4E VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VRSQRTPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VRSQRTPBF16 (VRSQRTPBF16-256-1)
{
ICLASS:      VRSQRTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x4E VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VRSQRTPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VRSQRTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x4E VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VRSQRTPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VRSQRTPBF16 (VRSQRTPBF16-512-1)
{
ICLASS:      VRSQRTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x4E VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VRSQRTPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VRSQRTPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x4E VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VRSQRTPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VSCALEFPBF16 (VSCALEFPBF16-128-1)
{
ICLASS:      VSCALEFPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x2C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VSCALEFPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x2C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VSCALEFPBF16 (VSCALEFPBF16-256-1)
{
ICLASS:      VSCALEFPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x2C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VSCALEFPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x2C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VSCALEFPBF16 (VSCALEFPBF16-512-1)
{
ICLASS:      VSCALEFPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x2C VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VSCALEFPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x2C VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


# EMITTING VSQRTNEPBF16 (VSQRTNEPBF16-128-1)
{
ICLASS:      VSQRTNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x51 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VSQRTNEPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VSQRTNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSQRTNEPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VSQRTNEPBF16 (VSQRTNEPBF16-256-1)
{
ICLASS:      VSQRTNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x51 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VSQRTNEPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VSQRTNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSQRTNEPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VSQRTNEPBF16 (VSQRTNEPBF16-512-1)
{
ICLASS:      VSQRTNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x51 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VSQRTNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VSQRTNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSQRTNEPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512
}


# EMITTING VSUBNEPBF16 (VSUBNEPBF16-128-1)
{
ICLASS:      VSUBNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
IFORM:       VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
}

{
ICLASS:      VSUBNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
}


# EMITTING VSUBNEPBF16 (VSUBNEPBF16-256-1)
{
ICLASS:      VSUBNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
IFORM:       VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
}

{
ICLASS:      VSUBNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
}


# EMITTING VSUBNEPBF16 (VSUBNEPBF16-512-1)
{
ICLASS:      VSUBNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x5C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16
IFORM:       VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
}

{
ICLASS:      VSUBNEPBF16
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_NE_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x5C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
}


