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# For reg/reg ops with rounding control, we have to avoid having the
#  RC bits mess up the length. So we fix them here.
FIX_ROUND_LEN256()::
mode16 | VL256 VL_IGN=1
mode32 | VL256 VL_IGN=1
mode64 | VL256 VL_IGN=1

AVX256_ROUND()::
BCRC=1 UBIT=0 LLRC=0b00 | ROUNDC=1 SAE=1
BCRC=1 UBIT=0 LLRC=0b01 | ROUNDC=2 SAE=1
BCRC=1 UBIT=0 LLRC=0b10 | ROUNDC=3 SAE=1
BCRC=1 UBIT=0 LLRC=0b11 | ROUNDC=4 SAE=1
#Default: otherwise | error

SAE256()::
BCRC=1 UBIT=0 | SAE=1
#Default: otherwise | error
