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EVEX_INSTRUCTIONS()::
# EMITTING TCVTROWD2PS (TCVTROWD2PS-512-1)
{
ICLASS:      TCVTROWD2PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x4A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=TMM_B3():r:tv:u32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32
}


# EMITTING TCVTROWD2PS (TCVTROWD2PS-512-2)
{
ICLASS:      TCVTROWD2PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=TMM_B3():r:tv:u32 IMM0:r:b
IFORM:       TCVTROWD2PS_ZMMf32_TMMu32_IMM8
}


# EMITTING TCVTROWPS2PBF16H (TCVTROWPS2PBF16H-512-1)
{
ICLASS:      TCVTROWPS2PBF16H
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2PBF16H_ZMMbf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2PBF16H (TCVTROWPS2PBF16H-512-2)
{
ICLASS:      TCVTROWPS2PBF16H
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2PBF16H_ZMMbf16_TMMf32_IMM8
}


# EMITTING TCVTROWPS2PBF16L (TCVTROWPS2PBF16L-512-1)
{
ICLASS:      TCVTROWPS2PBF16L
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2PBF16L_ZMMbf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2PBF16L (TCVTROWPS2PBF16L-512-2)
{
ICLASS:      TCVTROWPS2PBF16L
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x77 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2PBF16L_ZMMbf16_TMMf32_IMM8
}


# EMITTING TCVTROWPS2PHH (TCVTROWPS2PHH-512-1)
{
ICLASS:      TCVTROWPS2PHH
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2PHH (TCVTROWPS2PHH-512-2)
{
ICLASS:      TCVTROWPS2PHH
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8
}


# EMITTING TCVTROWPS2PHL (TCVTROWPS2PHL-512-1)
{
ICLASS:      TCVTROWPS2PHL
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2PHL (TCVTROWPS2PHL-512-2)
{
ICLASS:      TCVTROWPS2PHL
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x77 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8
}


# EMITTING TILEMOVROW (TILEMOVROW-512-1)
{
ICLASS:      TILEMOVROW
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=TMM_B3():r:tv:u8 IMM0:r:b
IFORM:       TILEMOVROW_ZMMu8_TMMu8_IMM8
}


# EMITTING TILEMOVROW (TILEMOVROW-512-2)
{
ICLASS:      TILEMOVROW
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x4A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=TMM_B3():r:tv:u8 REG2=GPR32_N():r:d:u32
IFORM:       TILEMOVROW_ZMMu8_TMMu8_GPR32u32
}


AVX_INSTRUCTIONS()::
# EMITTING T2RPNTLVWZ0 (T2RPNTLVWZ0-128-1)
{
ICLASS:      T2RPNTLVWZ0
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x6E VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ0_TMM2u16_MEMu16
}


# EMITTING T2RPNTLVWZ0RS (T2RPNTLVWZ0RS-128-1)
{
ICLASS:      T2RPNTLVWZ0RS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_MOVRS
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0xF8 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ0RS_TMM2u16_MEMu16
}


# EMITTING T2RPNTLVWZ0RST1 (T2RPNTLVWZ0RST1-128-1)
{
ICLASS:      T2RPNTLVWZ0RST1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_MOVRS
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0xF9 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ0RST1_TMM2u16_MEMu16
}


# EMITTING T2RPNTLVWZ0T1 (T2RPNTLVWZ0T1-128-1)
{
ICLASS:      T2RPNTLVWZ0T1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x6F VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ0T1_TMM2u16_MEMu16
}


# EMITTING T2RPNTLVWZ1 (T2RPNTLVWZ1-128-1)
{
ICLASS:      T2RPNTLVWZ1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x6E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ1_TMM2u16_MEMu16
}


# EMITTING T2RPNTLVWZ1RS (T2RPNTLVWZ1RS-128-1)
{
ICLASS:      T2RPNTLVWZ1RS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_MOVRS
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0xF8 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ1RS_TMM2u16_MEMu16
}


# EMITTING T2RPNTLVWZ1RST1 (T2RPNTLVWZ1RST1-128-1)
{
ICLASS:      T2RPNTLVWZ1RST1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_MOVRS
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0xF9 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ1RST1_TMM2u16_MEMu16
}


# EMITTING T2RPNTLVWZ1T1 (T2RPNTLVWZ1T1-128-1)
{
ICLASS:      T2RPNTLVWZ1T1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE
EXCEPTIONS:  AMX-E11
REAL_OPCODE: Y
ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x6F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
IFORM:       T2RPNTLVWZ1T1_TMM2u16_MEMu16
}


# EMITTING TCONJTCMMIMFP16PS (TCONJTCMMIMFP16PS-128-1)
{
ICLASS:      TCONJTCMMIMFP16PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_COMPLEX
EXCEPTIONS:  AMX-E10
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x6B VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2f16 REG2=TMM_N():r:tv:2f16
IFORM:       TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16
}


# EMITTING TCONJTFP16 (TCONJTFP16-128-1)
{
ICLASS:      TCONJTFP16
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_COMPLEX
EXCEPTIONS:  AMX-E9
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x6B V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:2f16 REG1=TMM_B():r:tv:2f16
IFORM:       TCONJTFP16_TMM2f16_TMM2f16
}


# EMITTING TDPBF8PS (TDPBF8PS-128-1)
{
ICLASS:      TDPBF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD VNP MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4bf8 REG2=TMM_N():r:tv:4bf8
IFORM:       TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8
}


# EMITTING TDPBHF8PS (TDPBHF8PS-128-1)
{
ICLASS:      TDPBHF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD VF2 MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4bf8 REG2=TMM_N():r:tv:4hf8
IFORM:       TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8
}


# EMITTING TDPHBF8PS (TDPHBF8PS-128-1)
{
ICLASS:      TDPHBF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD VF3 MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4hf8 REG2=TMM_N():r:tv:4bf8
IFORM:       TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8
}


# EMITTING TDPHF8PS (TDPHF8PS-128-1)
{
ICLASS:      TDPHF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD V66 MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4hf8 REG2=TMM_N():r:tv:4hf8
IFORM:       TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8
}


# EMITTING TILELOADDRS (TILELOADDRS-128-1)
{
ICLASS:      TILELOADDRS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_MOVRS
EXCEPTIONS:  AMX-E3
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x4A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADDRS_TMMu32_MEMu32
}


# EMITTING TILELOADDRST1 (TILELOADDRST1-128-1)
{
ICLASS:      TILELOADDRST1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_MOVRS
EXCEPTIONS:  AMX-E3
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x4A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADDRST1_TMMu32_MEMu32
}


# EMITTING TMMULTF32PS (TMMULTF32PS-128-1)
{
ICLASS:      TMMULTF32PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TF32
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x48 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:f32 REG2=TMM_N():r:tv:f32
IFORM:       TMMULTF32PS_TMMf32_TMMf32_TMMf32
}


# EMITTING TTCMMIMFP16PS (TTCMMIMFP16PS-128-1)
{
ICLASS:      TTCMMIMFP16PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_COMPLEX
EXCEPTIONS:  AMX-E10
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x6B VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2f16 REG2=TMM_N():r:tv:2f16
IFORM:       TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16
}


# EMITTING TTCMMRLFP16PS (TTCMMRLFP16PS-128-1)
{
ICLASS:      TTCMMRLFP16PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_COMPLEX
EXCEPTIONS:  AMX-E10
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x6B VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2f16 REG2=TMM_N():r:tv:2f16
IFORM:       TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16
}


# EMITTING TTDPBF16PS (TTDPBF16PS-128-1)
{
ICLASS:      TTDPBF16PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_BF16
EXCEPTIONS:  AMX-E10
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x6C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:bf16 REG2=TMM_N():r:tv:bf16
IFORM:       TTDPBF16PS_TMMf32_TMMbf16_TMMbf16
}


# EMITTING TTDPFP16PS (TTDPFP16PS-128-1)
{
ICLASS:      TTDPFP16PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_FP16
EXCEPTIONS:  AMX-E10
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x6C VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:f16 REG2=TMM_N():r:tv:f16
IFORM:       TTDPFP16PS_TMMf32_TMMf16_TMMf16
}


# EMITTING TTMMULTF32PS (TTMMULTF32PS-128-1)
{
ICLASS:      TTMMULTF32PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE_TF32
EXCEPTIONS:  AMX-E10
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x48 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:f32 REG2=TMM_N():r:tv:f32
IFORM:       TTMMULTF32PS_TMMf32_TMMf32_TMMf32
}


# EMITTING TTRANSPOSED (TTRANSPOSED-128-1)
{
ICLASS:      TTRANSPOSED
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TRANSPOSE
EXCEPTIONS:  AMX-E9
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x5F VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32 REG1=TMM_B():r:tv:u32
IFORM:       TTRANSPOSED_TMMu32_TMMu32
}


