u 8nT(nradxa,e20crockchip,rk3528 + 7Radxa E20Caliases=/pinctrl/gpio@ff610000C/pinctrl/gpio@ffaf0000I/pinctrl/gpio@ffb00000O/pinctrl/gpio@ffb10000U/pinctrl/gpio@ffb20000[/soc/ethernet@ffbe0000e/soc/i2c@ffa58000j/soc/mmc@ffbf0000o/soc/mmc@ffc30000t/soc/serial@ff9f0000cpus+cpu-mapcluster0core0|core1|core2|core3|cpu@0arm,cortex-a53cpupscicpu@1arm,cortex-a53cpupscicpu@2arm,cortex-a53cpupscicpu@3arm,cortex-a53cpupscifirmwarescmi arm,scmi-smĉ +protocol@14opp-table-cpuoperating-points-v2opp-1200000000G Y Y @opp-1416000000Tfr HH @opp-1608000000_"  @opp-1800000000kI ԼԼ @opp-2016000000x)  @opp-table-gpuoperating-points-v2,opp-300000000 Y YB@opp-500000000e Y YB@opp-600000000#F Y YB@opp-700000000)' B@opp-800000000/ ~~B@pinctrlrockchip,rk3528-pinctrl' +4 gpio@ff610000rockchip,gpio-banka r s ;GFVb n]gpio@ffaf0000rockchip,gpio-bank  ;IFVb n gpio@ffb00000rockchip,gpio-bank $ % ;KFVb @ n gpio@ffb10000rockchip,gpio-bank  ;LFVb ` n gpio@ffb20000rockchip,gpio-bank  ;NFVb n Jpcfg-pull-uppcfg-pull-nonepcfg-pull-none-drv-level-0pcfg-pull-none-drv-level-2pcfg-pull-up-drv-level-2pcfg-pull-none-smtarmclkemmcemmc-bus8Kemmc-clkLemmc-cmdMemmc-strbNethfephyfephym0-led-link=fephym0-led-spd>fspigpuhdmihsmi2c0i2c1i2c1m0-xfer 0i2c2i2c2m1-xfer 2i2c3i2c4i2c4-xfer 3i2c5i2c6i2c7i2c7-xfer 4i2s0i2s1jtagpciepdmpmupwm0pwm1pwm1m0-pins5pwm2pwm2m0-pins6pwm3pwm4pwm5pwm6pwm7pwrrefrgmiirgmii-miim Drgmii-rx-bus20Frgmii-tx-bus20Ergmii-rgmii-clk Grgmii-rgmii-bus@ Hscrsdio0sdio0-bus4@Osdio0-clkPsdio0-cmdQsdio1sdio1-bus4@ Rsdio1-clkSsdio1-cmdTsdmmcsdmmc-bus4@Usdmmc-clkVsdmmc-cmdWsdmmc-detXsdmmc-vol-ctrl-hbspdifspi0spi1tsi0tsi1uart0uart0m0-xfer /uart1uart2uart3uart4uart5uart6uart7ethernetgmac1-rstn-lIgpio-keysuser-key\ledslan-led-g ^sys-led-g_wan-led-g`psciarm,psci-1.0arm,psci-0.2smcreserved-memory+4shmem@10f000arm,scmi-shmem timerarm,armv8-timer0;   clock-xin24m fixed-clockn6xin24mclock-gmac50m fixed-clockgmac0soc simple-bus4+interrupt-controller@fed01000 arm,gic-400@ @ `  ; nqos@ff200000rockchip,rk3528-qossyscon qos@ff200080rockchip,rk3528-qossyscon qos@ff200100rockchip,rk3528-qossyscon  qos@ff200200rockchip,rk3528-qossyscon  qos@ff200280rockchip,rk3528-qossyscon  qos@ff200300rockchip,rk3528-qossyscon  qos@ff200380rockchip,rk3528-qossyscon  qos@ff210000rockchip,rk3528-qossyscon! qos@ff210080rockchip,rk3528-qossyscon! qos@ff220000rockchip,rk3528-qossyscon" qos@ff220080rockchip,rk3528-qossyscon" qos@ff240000rockchip,rk3528-qossyscon$ qos@ff250000rockchip,rk3528-qossyscon% qos@ff260000rockchip,rk3528-qossyscon& qos@ff270000rockchip,rk3528-qossyscon' qos@ff270080rockchip,rk3528-qossyscon' qos@ff270100rockchip,rk3528-qossyscon' qos@ff270200rockchip,rk3528-qossyscon' qos@ff270280rockchip,rk3528-qossyscon' qos@ff270300rockchip,rk3528-qossyscon' qos@ff270380rockchip,rk3528-qossyscon'  qos@ff270480rockchip,rk3528-qossyscon' !qos@ff270500rockchip,rk3528-qossyscon' "qos@ff280000rockchip,rk3528-qossyscon( #qos@ff280080rockchip,rk3528-qossyscon( $qos@ff280100rockchip,rk3528-qossyscon( %qos@ff280180rockchip,rk3528-qossyscon( &qos@ff280200rockchip,rk3528-qossyscon( 'qos@ff280280rockchip,rk3528-qossyscon( (qos@ff280300rockchip,rk3528-qossyscon( )qos@ff280380rockchip,rk3528-qossyscon( *qos@ff280400rockchip,rk3528-qossyscon( +syscon@ff340000rockchip,rk3528-vpu-grfsyscon4?syscon@ff348000$rockchip,rk3528-pipe-phy-grfsyscon4Zsyscon@ff360000rockchip,rk3528-vo-grfsyscon69clock-controller@ff4a0000rockchip,rk3528-cruJ t          z y  LL(Fq;;]Q沀eр Cׄ#FsY@e =xin24mgmac0I syscon@ff540000rockchip,rk3528-ioc-grfsysconT power-management@ff600000&rockchip,rk3528-pmusysconsimple-mfd` power-controller!rockchip,rk3528-power-controllerV+ power-domain@4 jVpower-domain@5jV qdisabledpower-domain@6jVpower-domain@7$j !"Vpower-domain@8$j#$%&'()*+Vgpu@ff700000"rockchip,rk3528-maliarm,mali-450p (@  =buscoreT;XYV\]Z["xgpgpmmupppp0ppmmu0pp1ppmmu1,  wqokay-spi@ff9c0000(rockchip,rk3528-spirockchip,rk3066-spi =spiclkapb_pclk ;..txrx + qdisabledspi@ff9d0000(rockchip,rk3528-spirockchip,rk3066-spi =spiclkapb_pclk ;..txrx + qdisabledserial@ff9f0000&rockchip,rk3528-uartsnps,dw-apb-uart  k=baudclkapb_pclk ;(. .qokaydefault/serial@ff9f8000&rockchip,rk3528-uartsnps,dw-apb-uart  =baudclkapb_pclk ;). .   qdisabledserial@ffa00000&rockchip,rk3528-uartsnps,dw-apb-uart  =baudclkapb_pclk ;*. .   qdisabledserial@ffa08000&rockchip,rk3528-uartsnps,dw-apb-uart  =baudclkapb_pclk ;+..  qdisabledserial@ffa10000&rockchip,rk3528-uartsnps,dw-apb-uart  1=baudclkapb_pclk ;,..  qdisabledserial@ffa18000&rockchip,rk3528-uartsnps,dw-apb-uart " =baudclkapb_pclk ;-..  qdisabledserial@ffa20000&rockchip,rk3528-uartsnps,dw-apb-uart % =baudclkapb_pclk ;...  qdisabledserial@ffa28000&rockchip,rk3528-uartsnps,dw-apb-uart ( =baudclkapb_pclk ;/..  qdisabledi2c@ffa50000(rockchip,rk3528-i2crockchip,rk3399-i2c  =i2cpclk ;= + qdisabledi2c@ffa58000(rockchip,rk3528-i2crockchip,rk3399-i2c  =i2cpclk ;> +qokaydefault0eeprom@50belling,bl24c16aatmel,24c16P1i2c@ffa60000(rockchip,rk3528-i2crockchip,rk3399-i2c j i =i2cpclk ;?default2+ qdisabledi2c@ffa68000(rockchip,rk3528-i2crockchip,rk3399-i2c  =i2cpclk ;@ + qdisabledi2c@ffa70000(rockchip,rk3528-i2crockchip,rk3399-i2c 3 2 =i2cpclk ;Adefault3 + qdisabledi2c@ffa78000(rockchip,rk3528-i2crockchip,rk3399-i2c  =i2cpclk ;B + qdisabledi2c@ffa80000(rockchip,rk3528-i2crockchip,rk3399-i2c  =i2cpclk ;C + qdisabledi2c@ffa88000(rockchip,rk3528-i2crockchip,rk3399-i2c 5 4 =i2cpclk ;Ddefault4 + qdisabledpwm@ffa90000(rockchip,rk3528-pwmrockchip,rk3328-pwm o n =pwmpclk qdisabledpwm@ffa90010(rockchip,rk3528-pwmrockchip,rk3328-pwm o n =pwmpclkqokaydefault5cpwm@ffa90020(rockchip,rk3528-pwmrockchip,rk3328-pwm  o n =pwmpclkqokaydefault6dpwm@ffa90030(rockchip,rk3528-pwmrockchip,rk3328-pwm0 o n =pwmpclk qdisabledpwm@ffa98000(rockchip,rk3528-pwmrockchip,rk3328-pwm r q =pwmpclk qdisabledpwm@ffa98010(rockchip,rk3528-pwmrockchip,rk3328-pwm r q =pwmpclk qdisabledpwm@ffa98020(rockchip,rk3528-pwmrockchip,rk3328-pwm  r q =pwmpclk qdisabledpwm@ffa98030(rockchip,rk3528-pwmrockchip,rk3328-pwm0 r q =pwmpclk qdisabledadc@ffae0000rockchip,rk3528-saradc =saradcapb_pclk ;  o saradc-apbqokay 7[ethernet@ffbd0000&rockchip,rk3528-gmacsnps,dwmac-4.20a0      >=stmmacethclk_mac_refmac_clk_rxmac_clk_txpclk_macaclk_mac;qtxmacirqeth_wake_irq,87rmii   stmmaceth'9@:Pa;t< qdisabledmdiosnps,dwmac-mdio+ethernet-phy@2ethernet-phy-ieee802.3-c22 "default=> 8stmmac-axi-config:rx-queues-config;queue0tx-queues-config<queue0ethernet@ffbe0000&rockchip,rk3528-gmacsnps,dwmac-4.20a (=stmmacethclk_mac_refpclk_macaclk_mac;y|xmacirqeth_wake_irq  a stmmaceth'?@@PaAtBqokayoutput,C 7rgmii-id1defaultDEFGHmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22defaultIN   2JCstmmac-axi-config@rx-queues-configAqueue0tx-queues-configBqueue0mmc@ffbf00000rockchip,rk3528-dwcmshcrockchip,rk3588-dwcmshc  ( n6 ( =corebusaxiblocktimer ;> defaultKLMN ( A B C D EcorebusaxiblocktimerqokayLVhw}17mmc@ffc100000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@  =biuciuciu-driveciu-sample ;> default OPQ  greset qdisabledmmc@ffc200000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@  =biuciuciu-driveciu-sample ;> default RST  hreset qdisabledmmc@ffc300000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@ ( '  =biuciuciu-driveciu-sample ;>рdefaultUVWX  resetZqokayLV1Ydma-controller@ffd60000arm,pl330arm,primecell@ ^ =apb_pclkl; .phy@ffdc0000rockchip,rk3528-naneng-combphy {( {  =refapbpipe  c ephyapb!,?>Z qdisabledchosenTserial0:1500000n8adc-keys adc-keys`[lbuttons}w@dbutton-maskromMASKROMgpio-keys gpio-keysdefault\button-user 8]USERleds gpio-ledsdefault ^_`led-lanofflan 8J netdevled-syson heartbeat 8J heartbeatled-wanoffwan 8Jnetdevregulator-0v9-vddregulator-fixedvdd_0v9 4F ^ varegulator-1v1-vcc-ddrregulator-fixedvcc_ddr 4F^varegulator-1v8-vccregulator-fixedvcc_1v8 4Fw@^w@v17regulator-3v3-vccregulator-fixedvcc_3v3 4F2Z^2Zva1regulator-5v0-vcc-sysregulator-fixed vcc5v0_sys 4FLK@^LK@aregulator-vccio-sdregulator-gpio 8Jdefaultb vccio_sdFw@^2Zw@2ZvaYregulator-vdd-armpwm-regulatorcavdd_arm 4F b^Shregulator-vdd-logicpwm-regulatorda vdd_logic 4F ^Y- compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4ethernet0i2c1mmc0mmc1serial0cpuregdevice_typeenable-methodclocksoperating-points-v2cpu-supplyphandlearm,smc-idshmem#clock-cellsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrangesinterruptsgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspower-domainsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsno-mapclock-frequencyclock-output-namesassigned-clocksassigned-clock-ratesclock-names#reset-cells#power-domain-cellspm_qosstatusinterrupt-namesresetsmali-supplydmasdma-namesreg-io-widthreg-shiftpinctrl-namespinctrl-0pagesizeread-onlyvcc-supply#pwm-cellsreset-names#io-channel-cellsvref-supplyphy-handlephy-modesnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-is-integratedsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useclock_in_outphy-supplyreset-assert-usreset-deassert-usreset-gpiosmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vno-sdno-sdionon-removablevmmc-supplyvqmmc-supplyfifo-depthrockchip,default-sample-phasecap-sd-highspeeddisable-wpsd-uhs-sdr104#dma-cellsarm,pl330-periph-burst#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltwakeup-sourcecolordefault-statefunctionlinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplystatespwmspwm-supplyregulator-settling-time-up-us