R8( h!google,hana-rev7mediatek,mt8173 +7Google Hanawl=laptopaliasesJ/soc/ovl@1400c000O/soc/ovl@1400d000T/soc/rdma@1400e000Z/soc/rdma@1400f000`/soc/rdma@14010000f/soc/wdma@14011000l/soc/wdma@14012000r/soc/color@14013000y/soc/color@14014000/soc/split@14018000/soc/split@14019000/soc/dpi@1401d000/soc/dsi@1401b000/soc/dsi@1401c000/soc/rdma@14001000/soc/rdma@14002000/soc/rsz@14003000/soc/rsz@14004000/soc/rsz@14005000/soc/wdma@14006000/soc/wrot@14007000/soc/wrot@14008000/soc/serial@11002000/soc/serial@11003000/soc/serial@11004000/soc/serial@11005000 /soc/mmc@11230000/soc/mmc@11240000/soc/mmc@11260000opp-table-0operating-points-v2$ opp-507000000,843 xopp-702000000,)׫3 opp-1001000000,; @3opp-1105000000,A@3ehopp-1209000000,H@3opp-1300000000,M|m3 opp-1508000000,YA3opp-1703000000,e3*opp-table-1operating-points-v2$ opp-507000000,843 `opp-702000000,)׫3 :opp-1001000000,; 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{disabledaudio-controller@11220000mediatek,mt8173-afe-pcmQ" Ua5Pdeybinfra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_b mn0O6$dmmc@11230000mediatek,mt8173-mmcQ# UG_ sourcehclk{okaydefaultstate_uhs7o8y @  09 <: `0& Immc@11240000mediatek,mt8173-mmcQ$ UHR sourcehclk{okaydefaultstate_uhs;o<y  W h u  0= <> *mmc@11250000mediatek,mt8173-mmcQ% UIR sourcehclk {disabledmmc@11260000mediatek,mt8173-mmcQ& UJu sourcehclk{okaydefaultstate_uhs?o@y  W h u   0A <B I +btmrvl@2marvell,sd8897-btQ w  dmwifiex@1marvell,sd8897Q & usb@11271000#mediatek,mt8173-mtu3mediatek,mtu3 Q'0( macippc U@ CDEa5 ^sys_ckref_ck +<{okay host Fusb@11270000'mediatek,mt8173-xhcimediatek,mtk-xhciQ'mac Usa5 ^sys_ckref_ck{okaydefaultG Ft-phy@11290000mediatek,mt8173-u3phyQ)+<{okayusb-phy@11290800Q)ref{okay$Cusb-phy@11290900Q) ref{okay$Dusb-phy@11291000Q)ref{okay$Esyscon@14000000mediatek,mt8173-mmsyssysconQa5 U &ׄp ;HH BH$Irdma@14001000-mediatek,mt8173-mdp-rdmamediatek,mt8173-mdpQIIa5 ZJ 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BH`merge@14017000mediatek,mt8173-disp-mergeQpa5Isplit@14018000mediatek,mt8173-disp-splitQa5Isplit@14019000mediatek,mt8173-disp-splitQa5Iufoe@1401a000mediatek,mt8173-disp-ufoeQ Ua5I BHdsi@1401b000mediatek,mt8173-dsiQ Ua5I$I%LenginedigitalhsI L ndphy{okayportsportendpointlM$%dsi@1401c000mediatek,mt8173-dsiQ Ua5I&I'Nenginedigitalhs N ndphy {disableddpi@1401d000mediatek,mt8173-dpiQ Ua5I(I)pixelenginepll{okayportendpointlO$Tpwm@1401e000mediatek,mt8173-disp-pwmQ xI!I mainmm{okaydefaultP$Zpwm@1401f000mediatek,mt8173-disp-pwmQ xI#I"mainmm {disabledmutex@14020000mediatek,mt8173-disp-mutexQ Ua5I BH 56larb@14021000mediatek,mt8173-smi-larbQ Qa5IIapbsmi$smi@14022000mediatek,mt8173-smi-commonQ a5IIapbsmi$Qod@14023000mediatek,mt8173-disp-odQ0I BH0hdmi@14025000mediatek,mt8173-hdmiQP U I,I-I.I/pixelpllbclkspdifdefaultR S nhdmi I  s0S{okay$cports+port@0QendpointlT$Oport@1QendpointlU$glarb@14027000mediatek,mt8173-smi-larbQp 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compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mdp-rdma0mdp-rdma1mdp-rsz0mdp-rsz1mdp-rsz2mdp-wdma0mdp-wrot0mdp-wrot1serial0serial1serial2serial3mmc0mmc1mmc2opp-sharedphandleopp-hzopp-microvoltcpudevice_typeregenable-methodcpu-idle-states#cooling-cellsdynamic-power-coefficientclocksclock-namesoperating-points-v2capacity-dmips-mhzproc-supplysram-supplyentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paraminterruptsinterrupt-affinitycpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionrangessizealignmentno-maparm,no-tick-in-suspend#reset-cellsmediatek,pctl-regmapgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsgpio-line-namespinmuxinput-enablebias-pull-downbias-disablebias-pull-upoutput-lowoutput-highdrive-strength#power-domain-cellsmediatek,infracfgdomain-supplystatusreg-namesresetsreset-namesinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-allowed-modesregulator-enable-ramp-delaymemory-regionmediatek,larbs#iommu-cellsmediatek,ibiasmediatek,ibias_up#phy-cells#mbox-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0avdd-supplycpvdd-supply#sound-dai-cellsrealtek,dmic1-data-pinrealtek,jd-modepowerdown-gpiosreset-gpiosvdd12-supplyvdd33-supplyremote-endpointpower-supplybacklightregulator-min-microampregulator-max-microamppowered-while-suspendedmediatek,pad-selectspi-max-frequencygoogle,cros-ec-spi-msg-delaywakeup-sourcegoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymap#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesbank0-supplybank1-supplyassigned-clocksassigned-clock-parentshid-descr-addrvcc-supplypower-domainspinctrl-1bus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-reseths400-ds-delaymediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-cmd-resp-sel-risingvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104cd-gpioswp-gpioskeep-power-in-suspendcap-sdio-irqcap-power-off-cardmarvell,wakeup-pinmarvell,wakeup-gap-msphysmediatek,syscon-wakeupdr_modevusb33-supplyassigned-clock-ratesmboxesmediatek,gce-client-regiommusmediatek,vpuphy-names#pwm-cellsmediatek,gce-eventsmediatek,smimediatek,syscon-hdmimediatek,vdecsyspwmsenable-gpiosstartup-delay-usenable-active-highgpiostdout-pathlabellinux,codelinux,input-typedebounce-intervalregulator-boot-onoff-on-delay-usmediatek,audio-codecmediatek,platformmediatek,mclksound-daiddc-i2c-bus