8X(  %,embedfire,lubancat-1rockchip,rk35667EmbedFire LubanCat 1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55psci%2@DQ^@p} cpu@100cpu,arm,cortex-a55psci%2@DQ^@p} cpu@200cpu,arm,cortex-a55psci%2@DQ^@p} cpu@300cpu,arm,cortex-a55psci%2@DQ^@p} l3-cache,cache'4@Fdisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smcՂ protocol@14hdmi-sound,simple-audio-cardHDMI i2s#=okaysimple-audio-card,codecDsimple-audio-card,cpuD pmu,arm,cortex-a55-pmu0NY psci ,arm,psci-1.0smcreserved-memory lshmem@10f000,arm,scmi-shmemstimer,arm,armv8-timer0N   zxin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob N_ sata-phy =disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob N` sata-phy =disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Nref_clksuspend_clkbus_clkotg utmi_wide =disabled usb2-phy8 ?high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Nref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide=okayinterrupt-controller@fd400000 ,arm,gic-v3 @F N MbsA}(l msi-controller@fd440000,arm,gic-v3-itsD]usb@fd800000 ,generic-ehci Nusb=okayusb@fd840000 ,generic-ohci Nusb=okayusb@fd880000 ,generic-ehci Nusb=okayusb@fd8c0000 ,generic-ohci Nusb=okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd[io-domains&,rockchip,rk3568-pmu-io-voltage-domain=okaysyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucruclock-controller@fdd20000,rockchip,rk3568-cruxin24m! 1G F]i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c N.- i2cpclk default =okayregulator@1c ,tcs,tcs4525jvdd_cpu 50!regulator-state-mem pmic@20,rockchip,rk809 "Nrk808-clkout1rk808-clkout2default#%=K$W$c$o${$$$$$regulatorsDCDC_REG1 vdd_logic pqregulator-state-mem DCDC_REG2vdd_gpu pqCregulator-state-mem DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu pqregulator-state-mem DCDC_REG5vcc_1v8w@w@regulator-state-mem LDO_REG1vdda0v9_image  Wregulator-state-mem LDO_REG2 vdda_0v9  regulator-state-mem LDO_REG3 vdda0v9_pmu  regulator-state-mem LDO_REG4 vccio_acodec2Z2Zregulator-state-mem LDO_REG5 vccio_sdw@2Zregulator-state-mem LDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem2ZLDO_REG7 vcca_1v8w@w@regulator-state-mem LDO_REG8 vcca1v8_pmuw@w@regulator-state-memw@LDO_REG9vcca1v8_imagew@w@Xregulator-state-mem SWITCH_REG1vcc_3v3regulator-state-mem SWITCH_REG2 vcc3v3_sd_regulator-state-mem serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Nt ,baudclkapb_pclk%%&default =disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk'default =disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(default =disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)default =disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk*default =disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller) power-domain@7=+)power-domain@8 =,-.)power-domain@9  =/01)power-domain@10 =234567)power-domain@11 =8)power-domain@13 =9)power-domain@14 =:;<)power-domain@15==>?@A)gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$N()' Djobmmugpugpubus=okayBTCvideo-codec@fdea0400,rockchip,rk3568-vpu NDvdpu aclkhclk`D iommu@fdea0800,rockchip,rk3568-iommu@ N aclkiface gDrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga NZaclkhclksclk&$% tcoreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu N@ aclkhclk`E iommu@fdee0800,rockchip,rk3568-iommu@ N? aclkiface gEmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Nd biuciuciu-driveciu-sampleрtreset =disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aN Dmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref tstmmaceth]FGH=okayrgmiioutput I %$!F1sY@defaultJKLMN:C LOmdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22Ostmmac-axi-configWaqFrx-queues-configGqueue0tx-queues-configHqueue0vop@fe040000 0@vopgamma-lut N(%aclkhclkdclk_vp0dclk_vp1dclk_vp2`P ]=okay,rockchip,rk3566-vop!Fports port@0 endpoint@2QYport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? N aclkifaceg =okayPdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi NDpclkdphyR tapb] =disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi NEpclkdphyS tapb] =disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  N-((iahbisfrcecrefdefault TUV ]=okayWXports port@0endpointYQport@1endpointZqos@fe128000,rockchip,rk3568-qossyscon +qos@fe138080,rockchip,rk3568-qossyscon :qos@fe138100,rockchip,rk3568-qossyscon ;qos@fe138180,rockchip,rk3568-qossyscon <qos@fe148000,rockchip,rk3568-qossyscon ,qos@fe148080,rockchip,rk3568-qossyscon -qos@fe148100,rockchip,rk3568-qossyscon .qos@fe150000,rockchip,rk3568-qossyscon 8qos@fe158000,rockchip,rk3568-qossyscon 2qos@fe158100,rockchip,rk3568-qossyscon 3qos@fe158180,rockchip,rk3568-qossyscon 4qos@fe158200,rockchip,rk3568-qossyscon 5qos@fe158280,rockchip,rk3568-qossyscon 6qos@fe158300,rockchip,rk3568-qossyscon 7qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon =qos@fe190280,rockchip,rk3568-qossyscon >qos@fe190300,rockchip,rk3568-qossyscon ?qos@fe190380,rockchip,rk3568-qossyscon @qos@fe190400,rockchip,rk3568-qossyscon Aqos@fe198000,rockchip,rk3568-qossyscon 9qos@fe1a8000,rockchip,rk3568-qossyscon /qos@fe1a8080,rockchip,rk3568-qossyscon 0qos@fe1a8100,rockchip,rk3568-qossyscon 1dfi@fe230000,rockchip,rk3568-dfi# N [pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<NKJIHGDsyspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpcib`"\\\\0AP_n]v pcie-phyTl @@tpipe =okay "^legacy-interrupt-controllerbM NH\mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Nb biuciuciu-driveciu-sampleрtreset=okay_default`abcmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Nc biuciuciu-driveciu-sampleрtreset =disabledspi@fe300000 ,rockchip,sfc0@ Nexvclk_sfchclk_sfcddefault =disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 N!{}| 1 n6 (|zy{}corebusaxiblocktimer=okay  default efgrng@fe388000,rockchip,rk3568-rng8@po coreahbm =disabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ N4!=A1FqFq?C9mclk_txmclk_rxhclkh txPQ ttx-mrx-m] =disabled i2s@fe410000,rockchip,rk3568-i2s-tdmA N5!EI1FqFqGK:mclk_txmclk_rxhclkhh rxtxRS ttx-mrx-m]default0ijklmnopqrst=okay "i2s@fe420000,rockchip,rk3568-i2s-tdmB N6!M1FqOO;mclk_txmclk_rxhclkhh txrxTttx-m]defaultuvwx =disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC N7SW<mclk_txmclk_rxhclkhh txrxUV ttx-mrx-m] =disabledpdm@fe440000,rockchip,rk3568-pdmD NLZYpdm_clkpdm_hclkh  rxyz{|}~defaultXtpdm-m =disabledspdif@fe460000,rockchip,rk3568-spdifF Nf mclkhclk_\h txdefault =disableddma-controller@fe530000,arm,pl330arm,primecellS@N  =  apb_pclk T%dma-controller@fe550000,arm,pl330arm,primecellU@N =  apb_pclk Thi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ N/HG i2cpclkdefault  =disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ N0JI i2cpclkdefault  =disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ N1LK i2cpclkdefault  =disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] N2NM i2cpclkdefault  =disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ N3PO i2cpclkdefault  =disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` N tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia NgRQspiclkapb_pclk%% txrxdefault   =disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib NhTSspiclkapb_pclk%% txrxdefault   =disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic NiVUspiclkapb_pclk%% txrxdefault   =disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid NjXWspiclkapb_pclk%% txrxdefault   =disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Nubaudclkapb_pclk%%default =disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Nv# baudclkapb_pclk%%default=okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Nw'$baudclkapb_pclk%%default =disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Nx+(baudclkapb_pclk%% default =disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Ny/,baudclkapb_pclk% % default =disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Nz30baudclkapb_pclk% % default =disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk N{74baudclkapb_pclk%%default =disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl N|;8baudclkapb_pclk%%default =disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm N}?<baudclkapb_pclk%%default =disabledthermal-zonescpu-thermal _d u tripscpu_alert0 p passivecpu_alert1 $ passivecpu_crit s  criticalcooling-mapsmap0 0 gpu-thermal _ u tripsgpu-threshold p passivegpu-target $ passivegpu-crit s  criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq Ns!1f@ `tsadcapb_pclk] sdefaultsleep  =okay  saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr N]saradcapb_pclk tsaradc-apb '=okay 9pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault =disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault =disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault =disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault =disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault =disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault =disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault =disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault =disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault =disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault =disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault =disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault =disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe!"1tphy E W m=okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe!%1tphy E W m=okayphy@fe870000,rockchip,rk3568-csi-dphyypclk mtapb] =disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz m tapb =disabledRmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ m tapb =disabledSusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m N x=okayhost-port m=okayotg-port m=okayusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m N x=okayhost-port m=okayotg-port m=okaypinctrl,rockchip,rk3568-pinctrl][ lgpio@fdd60000,rockchip,gpio-bank N!.    Mb"gpio@fe740000,rockchip,gpio-bankt N"cd   Mbgpio@fe750000,rockchip,gpio-banku N#ef  @  MbIgpio@fe760000,rockchip,gpio-bankv N$gh  `  Mbgpio@fe770000,rockchip,gpio-bankw N%ij   Mbpcfg-pull-up pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmcemmc-bus8   eemmc-clk femmc-cmd geth0eth1flashfspifspi-pins` dgmac0gmac1gmac1m1-miim Jgmac1m1-rx-bus20  Lgpuhdmitxhdmitxm0-cec Vhdmitx-scl Thdmitx-sda Ui2c0i2c0-xfer   i2c1i2c1-xfer  i2c2i2c2m0-xfer i2c3i2c3m0-xfer i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrckrx li2s1m0-lrcktx ki2s1m0-sclkrx ji2s1m0-sclktx ii2s1m0-sdi0  mi2s1m0-sdi1  ni2s1m0-sdi2  oi2s1m0-sdi3 pi2s1m0-sdo0 qi2s1m0-sdo1 ri2s1m0-sdo2  si2s1m0-sdo3  ti2s2i2s2m0-lrcktx vi2s2m0-sclktx ui2s2m0-sdi wi2s2m0-sdo xi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ypdmm0-clk1 zpdmm0-sdi0  {pdmm0-sdi1  |pdmm0-sdi2  }pdmm0-sdi3 ~pmicpmic_int #pmupwm0pwm0m0-pins 'pwm1pwm1m0-pins (pwm2pwm2m0-pins )pwm3pwm3-pins *pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ `sdmmc0-clk asdmmc0-cmd bsdmmc0-det csdmmc1sdmmc2spdifspdifm0-tx spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer &uart1uart1m0-xfer   uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac1m1-tx-bus2-level30 Kgmac1m1-rgmii-bus-level3@ Ngmac-txc-level2gmac1m1-rgmii-clk-level2 Mledssys-status-led-pin usbvcc5v0-usb20-host-en vcc5v0-usb30-host-en  opp-table-0,operating-points-v2 opp-408000000 Q  P P0 @opp-600000000 #F  P P0 @opp-816000000 0,  P P0 @ -opp-1104000000 Aʹ  0 @opp-1416000000 Tfr 0 @opp-1608000000 _" 0 @opp-1800000000 kI 000 @opp-table-1,operating-points-v2Bopp-200000000    P PB@opp-300000000   P PB@opp-400000000 ׄ  P PB@opp-600000000 #F  B@opp-700000000 )' ~~B@opp-800000000 / B@B@B@chosen 9serial2:1500000n8external-gmac1-clock ,fixed-clocksY@ gmac1_clkinhdmi-con,hdmi-connectoraportendpointZgpio-leds ,gpio-ledssys-led Esys_led Kheartbeat aon "defaultregulator-usb-5v,regulator-fixedusb_5vLK@LK@regulator-vcc5v0-sys,regulator-fixed vcc5v0_sysLK@LK@!regulator-vcc3v3-sys,regulator-fixed vcc3v3_sys2Z2Z!$regulator-vcc3v3-pcie,regulator-fixed vcc3v3_pcie2Z2Z o  " !^regulator-vcc5v0-usb20-host,regulator-fixed o  Idefaultvcc5v0_usb20_hostregulator-vcc5v0-usb30-host,regulator-fixed o  I defaultvcc5v0_usb30_host interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathlabellinux,default-triggerdefault-stateenable-active-highstartup-delay-us