V8( pine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@1cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@2cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@3cpuarm,cortex-a53xpsci@&3@@R_p{ idle-statespscicpu-sleeparm,idle-statex{l2-cachecache @({opp-table-0operating-points-v2{opp-408000000Q~$@5opp-600000000#F~$@opp-8160000000,B@$@opp-1008000000<$@opp-1200000000G($@opp-1296000000M?d $@analog-soundsimple-audio-cardAi2sZtAnalogokaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem hdmi-soundsimple-audio-cardAi2sZtHDMIokaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24m{Ii2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx okay{i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx okay{i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx  disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk txdefault* okay{lpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep*4 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd{Eio-domains"rockchip,rk3328-io-voltage-domainokay>LZhvgpiorockchip,rk3328-grf-gpio{Hpower-controller!rockchip,rk3328-power-controller+{;power-domain@1power-domain@6Dpower-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrxdefault * !  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrxdefault *"#$  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrxdefault*% okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclkdefault*& disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclkdefault*'okaypmic@18rockchip,rk805 (xin32krk805-clkout2default*)#;I*U*a*m*y*{kregulatorsDCDC_REG1 vdd_logic 4 0{<regulator-state-mem #B@DCDC_REG2vdd_arm 4 0{regulator-state-mem #~DCDC_REG3vcc_ddrregulator-state-mem DCDC_REG4vcc_io2Z2Z{regulator-state-mem #2ZLDO_REG1vcc_18w@w@{regulator-state-mem #w@LDO_REG2 vcc18_emmcw@w@{regulator-state-mem #w@LDO_REG3vdd_10B@B@{Fregulator-state-mem #B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclkdefault*+ disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclkdefault*, disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrxdefault*-./0okayflash@0jedec,spi-nor?Qwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault*1\ disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault*2\ disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault*3\ disabledpwm@ff1b0030rockchip,rk3328-pwm0< pwmpclkdefault*4\ disableddma-controller@ff1f0000arm,pl330arm,primecell@g apb_pclk~{thermal-zonessoc-thermal5tripstrip-point0ppassivetrip-point1Lpassive{6soc-crits criticalcooling-mapsmap060 map16 7tsadc@ff250000rockchip,rk3328-tsadc% :$P$tsadcapb_pclkinitdefaultsleep*849,86B =tsadc-apbI`okayv{5efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a{Jadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclk6V =saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore:;6f<{7opp-table-gpuoperating-points-v2{:opp-200000000 g8opp-300000000g8opp-400000000ׄg8opp-500000000e0 disablediommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk =;iommu@ff350800rockchip,iommu5@  F aclkiface;{=video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreAB ׄׄ >;iommu@ff360480rockchip,iommu 6@6@ JB aclkiface;{>vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop6 =axiahbdclk ?okayport{ endpoint@{Giommu@ff373f00rockchip,iommu7?  ; aclkifaceokay{?hdmi@ff3c0000rockchip,rk3328-dw-hdmi<  #Fiahbisfrcec!A&hdmidefault *BCD0E okay=FM{ports+port@0endpointG{@port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk0E okay ]H{phy@ff430000rockchip,rk3328-hdmi-phyC SIysysclkrefoclkrefpclk hdmi_phyhJ tcpu-versionokay{Aclock-controller@ff440000rockchip,rk3328-cruDIxin24m0Ex=&'(ABDC"\5H4$zIII|n6n6n6ׄn6#FLGрxhxhрxhxh{syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyIphyclk usb480m_phy{Kokay{Kotg-port$;<=otg-bvalidotg-idlinestateokay{Zhost-port > linestateokay{[mmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleCр6m=resetokaydefault*LMNOPmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleCр6n=reset disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleCр6o=resetokaydefault *QRS ethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac6c =stmmaceth0E-;IokaydfTTTinputalrgmiidefault*U uV 'P$ethernet@ff550000rockchip,rk3328-gmacU0E macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy6b =stmmacethlrmiiW-;IToutput disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V6ddefault*XY{Wusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost @ !Z &usb2-phyokayusb@ff5c0000 generic-ehci\  NK![&usbokayusb@ff5d0000 generic-ohci]  NK![&usbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-sampleCр6h=reset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkhost utmi_wide  A Y {  okayinterrupt-controller@ff811000 arm,gic-400  @ @ `   {crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclk6D =crypto-rstpinctrlrockchip,rk3328-pinctrl0E+ gpio@ff210000rockchip,gpio-bank! 3  {ggpio@ff220000rockchip,gpio-bank" 4  {Vgpio@ff230000rockchip,gpio-bank# 5  {(gpio@ff240000rockchip,gpio-bank$ 6  pcfg-pull-up {^pcfg-pull-down {fpcfg-pull-none {\pcfg-pull-none-2ma  ${epcfg-pull-up-2ma  $pcfg-pull-up-4ma  ${_pcfg-pull-none-4ma  ${bpcfg-pull-down-4ma  $pcfg-pull-none-8ma  ${`pcfg-pull-up-8ma  ${apcfg-pull-none-12ma  $ {cpcfg-pull-up-12ma  $ {dpcfg-output-high 3pcfg-output-low ?pcfg-input-high  J{]pcfg-input Ji2c0i2c0-xfer W\\{&i2c1i2c1-xfer W\\{'i2c2i2c2-xfer W \\{+i2c3i2c3-xfer W\\{,i2c3-pins W\\hdmi_i2chdmii2c-xfer W\\{Cpdm-0pdmm0-clk W\{pdmm0-fsync W\pdmm0-sdi0 W\{pdmm0-sdi1 W\{pdmm0-sdi2 W\{pdmm0-sdi3 W\{pdmm0-clk-sleep W]{pdmm0-sdi0-sleep W]{pdmm0-sdi1-sleep W]{pdmm0-sdi2-sleep W]{pdmm0-sdi3-sleep W]{pdmm0-fsync-sleep W]tsadcotp-pin W \{8otp-out W \{9uart0uart0-xfer W \^{uart0-cts W \{ uart0-rts W \{!uart0-rts-pin W \uart1uart1-xfer W\^{"uart1-cts W\{#uart1-rts W\{$uart1-rts-pin W\uart2-0uart2m0-xfer W\^uart2-1uart2m1-xfer W\^{%spi0-0spi0m0-clk W^spi0m0-cs0 W ^spi0m0-tx W ^spi0m0-rx W ^spi0m0-cs1 W ^spi0-1spi0m1-clk W^spi0m1-cs0 W^spi0m1-tx W^spi0m1-rx W^spi0m1-cs1 W^spi0-2spi0m2-clk W^{-spi0m2-cs0 W^{0spi0m2-tx W^{.spi0m2-rx W^{/i2s1i2s1-mclk W\i2s1-sclk W\i2s1-lrckrx W\i2s1-lrcktx W\i2s1-sdi W\i2s1-sdo W\i2s1-sdio1 W\i2s1-sdio2 W\i2s1-sdio3 W\i2s1-sleep W]]]]]]]]]i2s2-0i2s2m0-mclk W\i2s2m0-sclk W\i2s2m0-lrckrx W\i2s2m0-lrcktx W\i2s2m0-sdi W\i2s2m0-sdo W\i2s2m0-sleep` W]]]]]]i2s2-1i2s2m1-mclk W\i2s2m1-sclk W\i2sm1-lrckrx W\i2s2m1-lrcktx W\i2s2m1-sdi W\i2s2m1-sdo W\i2s2m1-sleepP W]]]]]spdif-0spdifm0-tx W\{spdif-1spdifm1-tx W\spdif-2spdifm2-tx W\sdmmc0-0sdmmc0m0-pwren W_sdmmc0m0-pin W_sdmmc0-1sdmmc0m1-pwren W_sdmmc0m1-pin W_{hsdmmc0sdmmc0-clk W`{Lsdmmc0-cmd Wa{Msdmmc0-dectn W_{Nsdmmc0-wrprt W_sdmmc0-bus1 Wasdmmc0-bus4@ Waaaa{Osdmmc0-pins W________sdmmc0extsdmmc0ext-clk Wbsdmmc0ext-cmd W_sdmmc0ext-wrprt W_sdmmc0ext-dectn W_sdmmc0ext-bus1 W_sdmmc0ext-bus4@ W____sdmmc0ext-pins W________sdmmc1sdmmc1-clk W `sdmmc1-cmd W asdmmc1-pwren Wasdmmc1-wrprt Wasdmmc1-dectn Wasdmmc1-bus1 Wasdmmc1-bus4@ Waaaasdmmc1-pins W _ ________emmcemmc-clk Wc{Qemmc-cmd Wd{Remmc-pwren W\emmc-rstnout W\emmc-bus1 Wdemmc-bus4@ Wddddemmc-bus8 Wdddddddd{Spwm0pwm0-pin W\{1pwm1pwm1-pin W\{2pwm2pwm2-pin W\{3pwmirpwmir-pin W\{4gmac-1rgmiim1-pins` W ` bb`bbb b b` `bb``` `b````{Urmiim1-pins Weceeee e ec c \ \\\\\gmac2phyfephyled-speed10 W\fephyled-duplex W\fephyled-rxm1 W\{Xfephyled-txm1 W\fephyled-linkm1 W\{Ytsadc_pintsadc-int W \tsadc-pin W \hdmi_pinhdmi-cec W\{Bhdmi-hpd Wf{Dcif-0dvp-d2d9-m0 W\\\\\ \ \ \\\\\cif-1dvp-d2d9-m1 W\\\\\\\\\\\\irir-int W\{jpmicpmic-int-l W^{)usb2usb20-host-drv W\{ichosen eserial2:1500000n8external-gmac-clock fixed-clocksY@ gmac_clkin{Tregulator-sdmmcregulator-fixed gdefault*hvcc_sd2Z2Z q{Pregulator-vcc-host-5vregulator-fixed gdefault*i vcc_host_5v q*regulator-vcc-sysregulator-fixedvcc_sysLK@LK@{*ir-receivergpio-ir-receiver b(*jdefaultleds gpio-ledsled-0 bk |mmc0led-1 bk |heartbeatspdif-soundsimple-audio-cardtSPDIFsimple-audio-card,cpulsimple-audio-card,codecmspdif-ditlinux,spdif-dit {m compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequencyvcc-supply#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domainsmali-supply#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfavdd-0v9-supplyavdd-1v8-supplymute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supplytx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplylinux,default-trigger