S8N (M ,Huawei Nexus 6P2huawei,anglerqcom,msm8994=handsetJV  cZaliasesq/soc@0/mmc@f9824900v/soc@0/mmc@f98a4900{/soc@0/serial@f991e000chosenserial0:115200n8clocksxo-board 2fixed-clock$ xo_boardsleep-clk 2fixed-clock sleep_clkcpus cpu@0cpu2arm,cortex-a53pscil2-cache2cachecpu@1cpu2arm,cortex-a53pscicpu@2cpu2arm,cortex-a53pscicpu@3cpu2arm,cortex-a53pscicpu@100cpu2arm,cortex-a57pscil2-cache2cachecpu@101cpu2arm,cortex-a57psci cpu@102cpu2arm,cortex-a57psci cpu@103cpu2arm,cortex-a57psci cpu-mapcluster0core0core1core2core3cluster1core0core1 core2 core3 firmwarescm2qcom,scm-msm8994qcom,scmmemory@80000000memorypmu2arm,cortex-a53-pmu psci 2arm,psci-0.2hvcremoteproc$2qcom,msm8994-rpm-procqcom,rpm-procsmd-edge  &4rpm-requests2qcom,rpm-msm8994qcom,smd-rpm Drpm_requestsclock-controller2qcom,rpmcc-msm8994qcom,rpmcc>power-controller2qcom,msm8994-rpmpdVj opp-table2operating-points-v2 opp1~opp2~opp3~opp4~opp5~opp6~reserved-memory dfps-data@3400000@memory@3401000@smem@6a00000 memory@7000000memory@ca00000 memory@c64000002qcom,rmtfs-mem@memory@c6700000pmemory@c7000000memory@c9400000@reserved@6c00000@tzapp@4800000reserved@63000000psmem 2qcom,smemsmp2p-lpass 2qcom,smp2p  4master-kernelmaster-kernelslave-kernel slave-kernel !smp2p-modem 2qcom,smp2p  4master-kernelmaster-kernelslave-kernel slave-kernel !soc@0  2simple-businterrupt-controller@f90000002qcom,msm-qgic2 ! mailbox@f900d000%2qcom,msm8994-apcs-kpss-globalsyscon 2 watchdog@f9017000$2qcom,apss-wdt-msm8994qcom,kpss-wdtp>E timer@f9020000 2arm,armv7-timer-memframe@f9021000Q  frame@f9023000Q  0 ^disabledframe@f9024000Q  @ ^disabledframe@f9025000Q  P ^disabledframe@f9026000Q  ` ^disabledframe@f9027000Q p ^disabledframe@f9028000Q  ^disabledusb@f92f88002qcom,msm8994-dwc3qcom,dwc3/ 076*epwr_eventqusb2_phyhs_phy_irqss_phy_irq >rmsucoreifacesleepmock_utmisr$'usb@f9200000 2snps,dwc3   high-speed peripheralmmc@f9824900%2qcom,msm8994-sdhciqcom,sdhci-msm-v4I@hccore{ehc_irqpwr_irq>vhuifacecorexo"defaultsleep0:DN^okay\mmc@f98a4900%2qcom,msm8994-sdhciqcom,sdhci-msm-v4I@hccore}ehc_irqpwr_irq>iuifacecorexo"defaultsleep 0 : ! k"dD ^disableddma-controller@f99040002qcom,bam-v1.7.0@ >:ubam_clkt%serial@f991e000%2qcom,msm-uartdm-v1.4qcom,msm-uartdm l ucoreiface>H:"defaultsleep0#:$^okayi2c@f99230002qcom,i2c-qup-v2.2.10 _>;: ucoreiface% % txrx"defaultsleep0&:'  ^disabledspi@f99230002qcom,spi-qup-v2.2.10 _><: ucoreiface% % txrx"defaultsleep0(:)  ^disabledi2c@f99240002qcom,i2c-qup-v2.2.1@ `>=: ucoreiface%%txrx"defaultsleep0*:+  ^disabledi2c@f99260002qcom,i2c-qup-v2.2.1` b>A: ucoreiface%%txrx"defaultsleep0,:-  ^disabledi2c@f99270002qcom,i2c-qup-v2.2.1p c>C: ucoreiface..txrx"defaultsleep0/:0  ^disabledi2c@f99280002qcom,i2c-qup-v2.2.1 d>E: ucoreiface%%txrx"defaultsleep01:2  ^disableddma-controller@f99440002qcom,bam-v1.7.0@ >Mubam_clkt.serial@f995e000%2qcom,msm-uartdm-v1.4qcom,msm-uartdm r ucoreiface>[M..txrx"defaultsleep03:4 ^disabledi2c@f99630002qcom,i2c-qup-v2.2.10 e>NM ucoreiface. . txrx"defaultsleep05:6  ^disabledspi@f99660002qcom,spi-qup-v2.2.1` h>UM ucoreiface..txrx"defaultsleep07:8  ^disabledi2c@f99670002qcom,i2c-qup-v2.2.1p i>VM ucoreifacej..txrx"defaultsleep09::  ^disabledclock-controller@fc4000002qcom,gcc-msm8994V@  uxosleep>sram@fc4280002qcom,rpm-msg-ramB@restart@fc4ab000 2qcom,psholdJspmi@fc4cf0002qcom,spmi-pmic-arbLLLcoreintrcnfg eperiph_irq   !pmic@02qcom,pm8994qcom,spmi-pmic rtc@60002qcom,pm8941-rtc`a rtcalarmapon@8002qcom,pm8916-ponpwrkey2qcom,pm8941-pwrkey=  tresin2qcom,pm8941-resin=  ^okayrtemp-alarm@24002qcom,spmi-temp-alarm$$";.thermal?@adc@31002qcom,spmi-vadc11 U;channel@7gxvph_pwrchannel@8 xdie_tempchannel@9  xref_625mvchannel@a  xref_1250mvchannel@echannel@fgpio@c000 2qcom,pm8994-gpioqcom,spmi-gpio~< !<mpps@a0002qcom,pm8994-mppqcom,spmi-mpp~= !=pmic@12qcom,pm8994qcom,spmi-pmic pwm2qcom,pm8994-lpg  ^disabledregulators2qcom,pm8994-regulatorshwlock@fd484000(2qcom,msm8994-tcsr-mutexqcom,tcsr-mutexH@pinctrl@fd5100002qcom,msm8994-pinctrlQ@ ~" !U"blsp1-uart2-default-state gpio4gpio5 blsp_uart2#blsp1-uart2-sleep-state gpio4gpio5gpio$blsp2-uart2-default-stategpio45gpio46gpio47gpio48 blsp_uart83blsp2-uart2-sleep-stategpio45gpio46gpio47gpio48gpio4i2c1-default-state gpio2gpio3 blsp_i2c1&i2c1-sleep-state gpio2gpio3gpio'i2c2-default-state gpio6gpio7 blsp_i2c2*i2c2-sleep-state gpio6gpio7gpio+i2c4-default-stategpio19gpio20 blsp_i2c4,i2c4-sleep-stategpio19gpio20gpio-i2c5-default-stategpio23gpio24 blsp_i2c5/i2c5-sleep-stategpio23gpio24gpio0i2c6-default-stategpio28gpio27 blsp_i2c61i2c6-sleep-stategpio28gpio27gpio2i2c7-default-stategpio44gpio43 blsp_i2c75i2c7-sleep-stategpio44gpio43gpio6blsp2-spi10-default-state7default-pinsgpio53gpio54gpio55 blsp_spi10 cs-pinsgpio67gpioblsp2-spi10-sleep-stategpio53gpio54gpio55gpio8i2c11-default-stategpio83gpio84 blsp_i2c119i2c11-sleep-stategpio83gpio84gpio:blsp1-spi1-default-state(default-pinsgpio0gpio1gpio3 blsp_spi1 cs-pinsgpio8gpioblsp1-spi1-sleep-stategpio0gpio1gpio3gpio)clk-on-state sdc1_clkclk-off-state sdc1_clkcmd-on-state sdc1_cmd cmd-off-state sdc1_cmd data-on-state sdc1_data data-off-state sdc1_data rclk-on-state sdc1_rclkrclk-off-state sdc1_rclksdc2-clk-on-state sdc2_clk sdc2-clk-off-state sdc2_clksdc2-cmd-on-state sdc2_cmd  sdc2-cmd-off-state sdc2_cmd  sdc2-data-on-state sdc2_data  sdc2-data-off-state sdc2_data !clock-controller@fd8c00002qcom,mmcc-msm8994RVYuxogpll0mmssnoc_ahboxili_gfx3d_clk_srcdsi0plldsi0pllbytedsi1plldsi1pllbytehdmipll0>>> (????? /E<98p#F?sram@fdd000002qcom,msm8974-ocmem  ctrlmem  >>"?r ucoreiface gmu-sram@0timer2arm,armv8-timer0vph-pwr-regulator2regulator-fixed vph_pwr646Lthermal-zonespm8994-thermal`v@tripspm8994-alert0sEpassivepm8994-critH Ecriticalgpio-keys 2gpio-keysbutton-vol-up xvolume up n<s interrupt-parent#address-cells#size-cellsmodelcompatiblechassis-typeqcom,msm-idqcom,pmic-idqcom,board-idmmc1mmc2serial0stdout-path#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregenable-methodnext-level-cachecache-levelcache-unifiedcpuinterruptsmboxesqcom,smd-edgeqcom,remote-pidqcom,smd-channels#power-domain-cellsoperating-points-v2opp-levelrangesno-mapqcom,client-idmemory-regionqcom,rpm-msg-ramhwlocksqcom,smemqcom,local-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cells#mbox-cellsclockstimeout-secframe-numberstatusinterrupt-namesclock-namesassigned-clocksassigned-clock-ratespower-domainsqcom,select-utmi-as-pipe-clksnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirkmaximum-speeddr_modereg-namespinctrl-namespinctrl-0pinctrl-1bus-widthnon-removablemmc-hs400-1_8vcd-gpios#dma-cellsqcom,eeqcom,controlled-remotelynum-channelsqcom,num-eesdmasdma-names#reset-cellsqcom,channelmode-bootloadermode-recoverydebouncebias-pull-uplinux,codeio-channelsio-channel-names#thermal-sensor-cells#io-channel-cellsqcom,pre-scalinglabelgpio-controllergpio-ranges#gpio-cells#pwm-cells#hwlock-cellsgpio-reserved-rangespinsfunctiondrive-strengthbias-disablebias-pull-downregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onpolling-delay-passivethermal-sensorstemperaturehysteresisautorepeatwakeup-sourcedebounce-interval