K8=(=-google,ciri-sku5google,cirimediatek,mt8188 +7Google Ciri sku5 board (rev4)aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dsc@1c009000T/soc/ethdr@1c114000[/soc/mailbox@10320000`/soc/mailbox@10330000e/soc/merge0@1c014000l/soc/merge@1c10c000s/soc/merge@1c10d000z/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000/soc/rdma@1c107000/soc/rdma@1c108000/soc/rdma@1c109000'/soc/rdma@1c10a0002/soc/rdma@1c10b000=/soc/dsi@1c008000B/soc/i2c@11280000G/soc/i2c@11e00000L/soc/i2c@11281000Q/soc/i2c@11282000V/soc/i2c@11e01000[/soc/i2c@11ec0000`/soc/i2c@11ec1000e/soc/mmc@11230000j/soc/serial@11001100cpus+cpu@0rcpuarm,cortex-a55~psciw5@@,@O cpu@100rcpuarm,cortex-a55~psciw5@@,@O cpu@200rcpuarm,cortex-a55~psciw5@@,@O cpu@300rcpuarm,cortex-a55~psciw5@@,@O cpu@400rcpuarm,cortex-a55~psciw5@@,@O cpu@500rcpuarm,cortex-a55~psciw5@@,@Ocpu@600rcpuarm,cortex-a78~psci@@,@Ocpu@700rcpuarm,cortex-a78~psci@@,@Ocpu-mapcluster0core0W core1W core2W core3W core4W core5Wcore6Wcore7Widle-states[pscicpu-off-larm,idle-stateh2_DOcpu-off-barm,idle-stateh-Ocluster-off-larm,idle-stateh7HOcluster-off-barm,idle-stateh2Ol2-cache0cache@Ol2-cache1cache@Ol3-cachecache @Ooscillator-13m fixed-clock]@clk13mO@oscillator-26m fixed-clockclk26mOCoscillator-32k fixed-clockclk32kopp-table-gpuoperating-points-v2Owopp-390000000>opp-431000000opp-4730000001h@ 'opp-515000000F Xopp-556000000!# hopp-598000000# <opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-8350000001 (ropp-8800000004s qopp-9150000006 Xopp-915000000-56 0opp-915000000-66 qpopp-9500000008ـ 5opp-950000000-58ـ X0opp-950000000-68ـ qppmu-a55arm,cortex-a55-pmu -pmu-a78arm,cortex-a78-pmu -psci arm,psci-1.0smcsound8Jokay]Qaud_etdm_hp_onaud_etdm_hp_offaud_etdm_spk_onaud_etdm_spk_offaud_mtkaif_onaud_mtkaif_off_is}mediatek,mt8188-es83267mt8188_tas2563_8326ETDM1_OUTETDM_SPK_PINETDM2_OUTETDM_HP_PINETDM1_INETDM_SPK_PINETDM2_INETDM_HP_PINADDA CaptureMTKAIF_PINHeadphone JackHPOLHeadphone JackHPORMIC1Headset Micdai-link-0 ETDM1_IN_BEi2scpudai-link-1 ETDM1_OUT_BEi2scpucodecdai-link-2 ETDM2_IN_BEcpucodecdai-link-3 ETDM2_OUT_BEcpucodecdai-link-4DPTX_BEcodecthermal-zonescpu-little0-thermaltripstrip-alert0 _,ypassiveO trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07 H< cpu-little1-thermaltripstrip-alert0 _,ypassiveO!trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07!H< cpu-little2-thermaltripstrip-alert0 _,ypassiveO"trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07"H< cpu-little3-thermaltripstrip-alert0 _,ypassiveO#trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07#H< cpu-big0-thermaldtripstrip-alert0 _,ypassiveO$trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07$<cpu-big1-thermaldtripstrip-alert0 _,ypassiveO%trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07%<apu-thermal&tripstrip-alert0 L,ypassivetrip-alert1 s,yhottrip-crit , ycriticalgpu-thermal&tripstrip-alert0 L,ypassiveO'trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07' <(gpu1-thermal&tripstrip-alert0 L,ypassiveO)trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07) <(adsp-thermal&tripstrip-alert0 L,ypassivetrip-alert1 s,yhottrip-crit , ycriticalvdo-thermal&tripstrip-alert0 L,ypassivetrip-alert1 s,yhottrip-crit , ycriticalinfra-thermal&tripstrip-alert0 L,ypassivetrip-alert1 s,yhottrip-crit , ycriticalcam1-thermal&tripstrip-alert0 L,ypassivetrip-alert1 s,yhottrip-crit , ycriticalcam2-thermal&tripstrip-alert0 L,ypassivetrip-alert1 s,yhottrip-crit , ycriticaltimerarm,armv8-timer @-   ]@soc+ simple-busKOperformance-controller@11bc10mediatek,cpufreq-hw ~ 0 VOinterrupt-controller@c000000 arm,gic-v3p  ~   - Oppi-partitionsinterrupt-partition-0 Ointerrupt-partition-1Osyscon@10000000 mediatek,mt8188-topckgensyscon~O-syscon@10001000#mediatek,mt8188-infracfg-aosyscon~O.syscon@10003000mediatek,mt8188-pericfgsyscon~0OWpinctrl@10005000mediatek,mt8188-pinctrl`~P0iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint*-pBGSC_AP_INT_ODLAP_DISP_BKLTENEN_PPVAR_MIPI_DISPEN_PPVAR_MIPI_DISP_150MATCHSCR_RST_1V8_LI2S_SPKR_DATAOUTEN_PP3300_WLAN_XWIFI_KILL_1V8_LBT_KILL_1V8_LAP_FLASH_WP_LWCAM_PWDN_LWCAM_RST_LUCAM_PWDM_LUCAM_RST_LWCAM_24M_CLKUCAM_24M_CLKMT6319_INTDISP_RST_1V8_LDSIO_DSI_TETPMIPI_BL_PWM_1V8UART_AP_TX_GSC_RXUART_GSC_TX_AP_RXUART_SSPM_TX_DBGCON_RXUART_DBGCON_TX_SSPM_RXUART_ADSP_TX_DBGCON_RXUART_DBGCON_TX_ADSP_RXJTAG_AP_TMSJTAG_AP_TCKJTAG_AP_TDIJTAG_AP_TDOJTAG_AP_TRSTAP_KPCOL0TPTPEC_AP_HPD_ODPCIE_WAKE_1V8_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLAP_I2C_AUD_SCL_1V8AP_I2C_AUD_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TPM_SDA_1V8AP_I2C_TCHSCR_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_PMIC_SAR_SCL_1V8AP_I2C_PMIC_SAR_SDA_1V8AP_I2C_EC_HID_KB_SCL_1V8AP_I2C_EC_HID_KB_SDA_1V8AP_I2C_UCAM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_WCAM_SCL_1V8AP_I2C_WCAM_SDA_1V8SPI_AP_CS_EC_LSPI_AP_CLK_ECSPI_AP_DO_EC_DISPI_AP_DI_EC_DOTPTPSPI_AP_CS_TCHSCR_LSPI_AP_CLK_TCHSCRSPI_AP_DO_TCHSCR_DISPI_AP_DI_TCHSCR_DOTPTPTPTPTPPWRAP_SPI_CS_LPWRAP_SPI_CKPWRAP_SPI_MOSIPWRAP_SPI_MISOSRCLKENA0SRCLKENA1SCP_VREQ_VAOAP_RTC_CLK32KAP_PMIC_WDTRST_LAUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1HP_INT_ODLSPKR_INT_ODLI2S_HP_DATAINEN_SPKRI2S_SPKR_MCLKI2S_SPKR_BCLKI2S_HP_MCLKI2S_HP_BCLKI2S_HP_LRCKI2S_HP_DATAOUTRST_SPKR_LI2S_SPKR_LRCKI2S_SPKR_DATAINSPI_AP_CLK_ROMSPI_AP_CS_ROM_LSPI_AP_DO_ROM_DISPI_AP_DI_ROM_DOTPTPEN_PP2800A_UCAM_XEN_PP1200_UCAM_XEN_PP2800A_WCAM_XEN_PP1100_WCAM_XTCHSCR_INT_1V8_LMT7921_PMU_EN_1V8AP_EC_WARM_RST_REQEC_AP_HID_INT_ODLEC_AP_INT_ODLAP_XHCI_INIT_DONEEMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RST_LEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLUSB3_HUB_RST_LEC_AP_RSVD0_ODLSPMI_SCLSPMI_SDAO*adsp-uart-pinsOKpins-bus#$aud-etdm-hp-on-pinsOpins-busnstupins-mclkraud-etdm-hp-off-pinsOpins-busnstu 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`Lxldo_vsim29vsim2H`/M`ldo_vsram_others_sshub9vsram_others_sshubH `rtcmediatek,mt6358-rtcspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi ~p pmifspmimst$-84-..-8(pmif_sys_ckpmif_tmr_ckspmimst_clk_muxiommu@10315000mediatek,mt8188-iommu-infra~1P-KOjmailbox@10320000mediatek,mt8188-gce~2@-X.Oxmailbox@10330000mediatek,mt8188-gce~3@-X.Ozscp@10720000mediatek,mt8188-scp-dual~rcfg+OPJokayscp@0mediatek,scp-core~ sram-JokayQdefault_Admediatek/mt8188/scp.imgrBO{scp@d0000mediatek,scp-core~ sram- Jdisabledaudio-controller@10b10000mediatek,mt8188-afe~$-S4-C, , ------S-- -E-Q-M-N-O-P?----T-Rclk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iec-6D E audiosys.-JokayrFOadsp@10b80000mediatek,mt8188-dsp@~ cfgsramsecbus$-D-D-Eaudiodspadsp_busGHrxtxD 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0Yethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10a~@- >-A-B-C> .axiapbmac_mainptp_refrmii_internalmac_cg$-A-B-C4---D L. ]Z m[ \    Jdisabledmdiosnps,dwmac-mdio+stmmac-axi-config   OZrx-queues-config  O[queue0  queue1  queue2  queue3  tx-queues-config 2 HO\queue0  Z hqueue1  Z hqueue2  Z hqueue3  Z hmmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc ~#- -...M!sourcehclksource_cgcrypto_clkJokay t ~  H       Qdefaultstate_uhs_]i^  _ `mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc ~$--..$sourcehclksource_cg$-4- Jdisabledmmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc ~%--..Asourcehclksource_cg$-4- Jdisabledthermal-sensor@11278000mediatek,mt8188-lvts-mcu~'-..Olvts-calib-data-1Oi2c@11280000mediatek,mt8188-i2c ~("- *a.7 maindma+JokayQdefault_baudio-codec@19everest,es8326~ *lQdefault_c 4 EOamplifier@4fti,tas2563ti,tas2781~OL [*vOi2c@11281000mediatek,mt8188-i2c ~("- *a.7 maindma+JokayQdefault_di2c@11282000mediatek,mt8188-i2c ~( "- *a.7 maindma+JokayQdefault_eclock-controller@11283000mediatek,mt8188-imp-iic-wrap-c~(0Oausb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 ~*-*> macippcO*?+-$--4-v>->sys_ckref_ckmcu_ckf WpJokay host "Xusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci~mac-$-.4-v>sys_ckJokay gusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 ~+-+> macippcO+?+-$-,4-v>->sys_ckref_ckmcu_ckg W`Jokay host "Xusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci~mac-$-+4-v>sys_ckJokay 0hpcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie~/  pcie-macO  xrpci +0.L.#.&.+.C> /pl_250mtl_26mtl_96mtl_32kperi_26mperi_memp-` iiii  j k pcie-phyDEmacJokayQdefault_linterrupt-controllerpOispi@1132c000(mediatek,mt8188-normediatek,mt8186-nor~2-X>> spisfaxi$-X-9+JokayQdefault_mflash@0jedec,spi-nor~ut-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3O+DJokaypcie-phy@0~-ref Okdsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx~C mipi_tx0_pll Jokay POdsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx~C mipi_tx0_pll  JdisabledOi2c@11e00000mediatek,mt8188-i2c ~"- *n.7 maindma+JokayQdefault_otpm@50 google,cr50~P *Qdefault_pi2c@11e01000mediatek,mt8188-i2c ~"- *n.7 maindma+JokayQdefault_qclock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w~ Ont-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+OJokayusb-phy@0~-, refda_ref Ogt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+OJokayusb-phy@0~-, refda_ref OUusb-phy@700~ ,C refda_ref OVt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+OJokayusb-phy@0~-, refda_ref Ofi2c@11ec0000mediatek,mt8188-i2c ~"- *r.7 maindma+JokayQdefault_si2c@11ec1000mediatek,mt8188-i2c ~"- *r.7 maindma+JokayQdefault_tclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en~ Orefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse~+dp-calib@1a0~ Olvts1-calib@1ac~@OOgpu-speedbin@581~ Ovsocinfo-data1@7a0~socinfo-data2@7e0~gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm~@u0-~} postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask~1-D Dxports+port@0~endpoint Oport@1~endpoint Osyscon@1c01d000mediatek,mt8188-vdosys0syscon~ x DxO1port+endpoint@0~ Osmi@1c022000mediatek,mt8188-smi-larb~ 11apbsmiD } Osmi@1c023000mediatek,mt8188-smi-larb~011apbsmiD } |O}smi@1c024000mediatek,mt8188-smi-common-vdo~@11apbsmiDOiommu@1c028000mediatek,mt8188-iommu-vdo~P1bclk-DK Osyscon@1c100000mediatek,mt8188-vdosys1syscon~ x DxO;port+endpoint@1~ Omutex@1c101000mediatek,mt8188-disp-mutex~;-D Dx \smi@1c102000mediatek,mt8188-smi-larb~ ;;apbsmiD } Osmi@1c103000mediatek,mt8188-smi-larb~0;;apbsmiD } |O~rdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~@;- =@D 2 Dx@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~P;- =y`D 2 DxPrdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~`;- =AD 2 Dx`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~p;- =yaD 2 Dxprdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~;- =BD 2 Dxrdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~;- =ybD 2 Dxrdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~;- =CD 2 Dxrdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~;- =ycD 2 Dxmerge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-D; Dx merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-D; Dx merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-D; Dx merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-D; Dx merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-D; Dx ports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Odp-intf@1c113000mediatek,mt8188-dp-intf~0;:;,pixelenginepll-DJokayports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Oethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp~@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh;0;+;.;,;/;-;<;1;2;3;4;5-mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top-6 =ydyeD(;1;2;3;4;5p Dx@xPxpxxxxports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Opadding@1c11d000mediatek,mt8188-disp-padding~;D Dxpadding@1c11e000mediatek,mt8188-disp-padding~; D Dxpadding@1c11f000mediatek,mt8188-disp-padding~;!D Dxpadding@1c120000mediatek,mt8188-disp-padding~;"D Dxpadding@1c121000mediatek,mt8188-disp-padding~;#D Dxpadding@1c122000mediatek,mt8188-disp-padding~ ;$D Dx padding@1c123000mediatek,mt8188-disp-padding~0;%D Dx0padding@1c124000mediatek,mt8188-disp-padding~@;&D Dx@edp-tx@1c500000mediatek,mt8188-edp-tx~P-dp_calibration_dataD + Jdisableddp-tx@1c600000mediatek,mt8188-dp-tx~`-dp_calibration_dataD +JokayQdefault_Oports+port@0~endpoint Oport@1~endpoint <backlight-lcd0pwm-backlight G Y@ * r   Ochosen serial0:115200n8dmic-codec dmic-codec  dmemory@40000000rmemory~@regulator-pp1800-ldo-z1regulator-fixed9pp1800_ldo_z1 Hw@`w@ hregulator-pp3300-s3regulator-fixed 9pp3300_s3 H2Z`2Z hOXregulator-pp3300-z1regulator-fixed 9pp3300_z1 H2Z`2Z Ohregulator-pp3300-wlanregulator-fixed 9pp3300_wlanH2Z`2Z  * _Qdefault hregulator-pp4200-s5regulator-fixed 9pp4200_s5 H@@`@@ regulator-pp5000-z1regulator-fixed 9pp5000_z1 HLK@`LK@ Oregulator-pp5000-usb-vbusregulator-fixed9pp5000_usb_vbusHLK@`LK@  * OYregulator-ppvar-sysregulator-fixed 9ppvar_sys Oregulator-ppvar-mipi-disp-avddregulator-fixed9ppvar_mipi_disp_avdd  *Qdefault_ Oregulator-ppvar-mipi-disp-aveeregulator-fixed9ppvar_mipi_disp_aveex'  *Qdefault_ Oreserved-memory+Omemory@50000000shared-dma-pool~P OBmemory@55000000shared-dma-pool~U@memory@60000000shared-dma-pool~` OJmemory@60f00000shared-dma-pool~` OFmemory@61000000shared-dma-pool~a OI compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0pinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5mediatek,adspaudio-routinglink-namedai-formatmediatek,clk-providersound-daipolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-downinput-enabledrive-strengthoutput-highbias-disableoutput-lowbias-pull-up#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadregulator-microvolt-offsetassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsfirmware-namememory-regionpower-domainsresetsreset-namesmediatek,topckgenmediatek,etdm-out1-cowork-sourcemediatek,etdm-in2-cowork-sourcemboxesmbox-namesspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdno-sdionon-removablesupports-cqevmmc-supplyvqmmc-supplyclock-diveverest,jack-poleverest,interrupt-clkreset-gpiosusb2-lpm-disablebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsdrive-strength-microampbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointenable-gpiosbacklightavdd-supplyavee-supplypp1800-supplyrotationmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanesbrightness-levelsdefault-brightness-levelnum-interpolated-stepspower-supplypwmsstdout-pathnum-channelswakeup-delay-msregulator-boot-onvin-supplyenable-active-highgpiono-map