?!8;(A;apm,merlinapm,xgene-shadowcat +7APM X-Gene Merlin boardcpus+cpu@0=cpu apm,stregaI Mspin-table[l}cpu@1=cpu apm,stregaI Mspin-table[l}cpu@100=cpu apm,stregaI Mspin-table[l}cpu@101=cpu apm,stregaI Mspin-table[l}cpu@200=cpu apm,stregaI Mspin-table[l}cpu@201=cpu apm,stregaI Mspin-table[l}cpu@300=cpu apm,stregaI Mspin-table[l} cpu@301=cpu apm,stregaI Mspin-table[l} l2-cache-0cachel2-cache-1cachel2-cache-2cachel2-cache-3cacheinterrupt-controller@78090000arm,cortex-a15-gic+  y@Ix x x xv2m@0arm,gic-v2m-frameIv2m@10000arm,gic-v2m-frameIv2m@20000arm,gic-v2m-frameIv2m@30000arm,gic-v2m-frameIv2m@40000arm,gic-v2m-frameIv2m@50000arm,gic-v2m-frameIv2m@60000arm,gic-v2m-frameIv2m@70000arm,gic-v2m-frameIv2m@80000arm,gic-v2m-frameIv2m@90000arm,gic-v2m-frameI v2m@a0000arm,gic-v2m-frameI v2m@b0000arm,gic-v2m-frameI v2m@c0000arm,gic-v2m-frameI v2m@d0000arm,gic-v2m-frameI v2m@e0000arm,gic-v2m-frameIv2m@f0000arm,gic-v2m-frameIclock-100000000 fixed-clock refclk pmuarm,armv8-pmuv3  timerarm,armv8-timer0 i2cslimproapm,xgene-slimpro-i2c hwmonslimproapm,xgene-slimpro-hwmon soc simple-bus+clocks+pmdpll@170000f0apm,xgene-pcppll-v2-clock} I pmdpll pmd0clk@7e200200apm,xgene-pmd-clock} I~  pmd0clkpmd1clk@7e200210apm,xgene-pmd-clock} I~  pmd1clkpmd2clk@7e200220apm,xgene-pmd-clock} I~   pmd2clkpmd3clk@7e200230apm,xgene-pmd-clock} I~ 0 pmd3clk socpll@17000120apm,xgene-socpll-v2-clock} I  socpll socplldiv2fixed-factor-clock} $/  socplldiv2ahbclk@17000000apm,xgene-device-clock}I 9div-regCdR` ahbclksbapbclk@1704c000apm,xgene-device-clock}I 9div-regCR`  sbapbclksdioclk@1f2ac000apm,xgene-device-clock} I* 9csr-regdiv-regnyCxR` sdioclkpcie0clk@1f2bc000apm,xgene-device-clock}I+9csr-reg  pcie0clkpcie1clk@1f2cc000apm,xgene-device-clock}I,9csr-reg  pcie1clkxge0clk@1f61c000apm,xgene-device-clock}Ia9csr-regy xge0clkxge1clk@1f62c000apm,xgene-device-clock}Ib9csr-regy xge1clkrngpkaclk@17000000apm,xgene-device-clock}I 9csr-regn y  rngpkaclki2c4clk@1704c000apm,xgene-device-clock}I9csr-regny@@ i2c4clksystem-clk-controller@17000000apm,xgene-scusysconIreboot@17000014syscon-rebootK}csw@7e200000apm,xgene-cswsysconI~ mcba@7e700000apm,xgene-mcbsysconI~pmcbb@7e720000apm,xgene-mcbsysconI~refuse@1054a000apm,xgene-efusesysconIT edac@78800000apm,xgene-edac+Ix$ !'edacmc@7e800000apm,xgene-edac-mcI~edacmc@7e840000apm,xgene-edac-mcI~edacmc@7e880000apm,xgene-edac-mcI~edacmc@7e8c0000apm,xgene-edac-mcI~edacpmd@7c000000apm,xgene-edac-pmdI| edacpmd@7c200000apm,xgene-edac-pmdI| edacpmd@7c400000apm,xgene-edac-pmdI|@ edacpmd@7c600000apm,xgene-edac-pmdI|` edacl3@7e600000apm,xgene-edac-l3-v2I~`edacsoc@7e930000apm,xgene-edac-socI~pmu@78810000apm,xgene-pmu-v2+Ix "pmul3c@7e610000apm,xgene-pmu-l3cI~apmuiob@7e940000apm,xgene-pmu-iobI~pmucmcb@7e710000apm,xgene-pmu-mcbI~qpmucmcb@7e730000apm,xgene-pmu-mcbI~spmucmc@7e810000apm,xgene-pmu-mcI~pmucmc@7e850000apm,xgene-pmu-mcI~pmucmc@7e890000apm,xgene-pmu-mcI~pmucmc@7e8d0000apm,xgene-pmu-mcI~mailbox@10540000apm,xgene-slimpro-mboxIT` serial@10600000ns16550I`  Lokayusb@19000000 disabled snps,dwc3I ]"/hostpcie@1f2b0000 disabled=pciapm,xgene-pcie+ I+9csrcfgT C 87BBBL_"}mpcie@1f2c0000 disabled=pciapm,xgene-pcie+ I,9csrcfgT C87BBBL_"}msata@1a000000apm,xgene-ahci-v2@I    Z"okaysata@1a200000apm,xgene-ahci-v2@I !!! ["okaysata@1a400000apm,xgene-ahci-v2@I@""" \"okaymmc@1c000000arasan,sdhci-4.9aI I"xclk_xinclk_ahb}okaygpio@1f63c000apm,xgene-gpioIc@gpio@1c024000snps,dw-apb-gpioI@+gpio-controller@0snps,dw-apb-gpio-port Igpio@17001000apm,xgene-gpio-sbI`()*+,-./ mdio@1f610000apm,xgene-mdio-xfi+Ia}phy@0Iethernet@1f610000apm,xgene2-sgenetokay0Ia` `a"}ssgmiiethernet@1f620000apm,xgene2-xgenetokay0Ib` "`lmnopqrs "}sxgmiirng@10520000apm,xgene-rngIR A}i2c@10511000+snps,designware-i2cIQ E}i2c@10640000+snps,designware-i2cId :}rtc@68dallas,ds1337Ihokaychosenmemory@100000000=memoryIgpio-keys gpio-keysbuttonPOWER%t0 poweroff_mbox@10548000#apm,merlin-poweroff-mailboxsysconIT0 poweroff@10548010syscon-poweroff K} compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeregenable-methodcpu-release-addrnext-level-cacheclockscache-levelcache-unifiedphandle#interrupt-cellsinterrupt-controllerinterruptsrangesmsi-controller#clock-cellsclock-frequencyclock-output-namesmboxesclock-multclock-divreg-namesdivider-offsetdivider-widthdivider-shiftcsr-offsetcsr-maskenable-offsetenable-maskregmapregmap-cswregmap-mcbaregmap-mcbbregmap-efusememory-controllerpmd-controllerenable-bit-index#mbox-cellsreg-shiftstatusdma-coherentdr_modedma-rangesbus-rangeinterrupt-map-maskinterrupt-mapmsi-parentno-1-8-vclock-namesgpio-controller#gpio-cellssnps,nr-gpiosapm,nr-gpiosapm,nr-irqsapm,irq-startlocal-mac-addressphy-connection-typephy-handlechannelport-idlabellinux,codelinux,input-type