+8(T(|("amd,seattle-overdriveamd,seattle +37AMD Seattle (Rev.B0) Development Board (Overdrive)clock-100000000 fixed-clock=JZadl3clk_100mhzmclock-375000000 fixed-clock=JZ Zccpclk_375mhzclock-333000000 fixed-clock=J-@Zsataclk_333mhzmclock-500000000 fixed-clock=JeZpcieclk_500mhzclock-250000000 fixed-clock=J沀Zmiscclk_250mhzminterrupt-controller@e1101000arm,gic-400arm,cortex-a15-gicu+@     mv2m@e0080000arm,gic-v2m-framemtimerarm,armv8-timer0   bus simple-bus+sata@e0300000snps,dwc-ahci0 c sata@e0d00000 disabledsnps,dwc-ahci biommu@e0200000 arm,mmu-401 LLmiommu@e0c00000 arm,mmu-401KKmi2c@e1000000okaysnps,designware-i2c ei2c@e0050000okaysnps,designware-i2c Tserial@e1010000arm,pl011arm,primecell H uartclkapb_pclkspi@e1020000okayarm,pl022arm,primecell J sspclkapb_pclkspi@e1030000okayarm,pl022arm,primecell I sspclkapb_pclk+mmc@0 mmc-spi-slot 1-2 HAQ`tgpio@e1040000 disabledarm,pl061arm,primecell gu  apb_pclkgpio@e1050000okayarm,pl061arm,primecellu f  apb_pclkgpio@e0020000 disabledarm,pl061arm,primecellu n  apb_pclkgpio@e0030000 disabledarm,pl061arm,primecellu m  apb_pclkgpio@e0080000okayarm,pl061arm,primecellu i  apb_pclkccp@e0100000okayamd,ccp-seattle-v1a  @Bpcie@f0000000pci-host-ecam-generic+pci !"#$%&'()*+CT@@okayiommu@e0a00000 arm,mmu-401MMmccn@e8000000 arm,ccn-504 |kcs@e0010000 disabled ipmi-kcsipmi ethernet@e0700000amd,xgbe-seattle-v1aPpx$%`%HEZ[\]C - = Q  d v  dma_clkptp_clkxgmii ethernet@e0900000amd,xgbe-seattle-v1aP$ %`%HDUVWXB - = Q  d v  dma_clkptp_clkxgmii iommu@e0600000 arm,mmu-401`PPm iommu@e0800000 arm,mmu-401OOm cpus+cpu-mapcluster0core0 core1 cluster1core0 core1cluster2core0core1cluster3core0core1cpu@0cpuarm,cortex-a57psci@ @)m cpu@1cpuarm,cortex-a57psci@ @)m cpu@100cpuarm,cortex-a57psci@ @)m cpu@101cpuarm,cortex-a57psci@ @)mcpu@200cpuarm,cortex-a57psci@ @)mcpu@201cpuarm,cortex-a57psci@ @)mcpu@300cpuarm,cortex-a57psci@ @)mcpu@301cpuarm,cortex-a57psci@ @)ml2-cache0@2@ml2-cache1@2@ml2-cache2@2@ml2-cache3@2@ml3-cacheQ@ 2mpmuarm,cortex-a57-pmu`      ] chosenp/bus/serial@e1010000psci arm,psci-0.2smc compatibleinterrupt-parent#address-cells#size-cellsmodel#clock-cellsclock-frequencyclock-output-namesphandleinterrupt-controller#interrupt-cellsreginterruptsrangesmsi-controllerdma-rangesclocksiommusdma-coherentstatus#global-interrupts#iommu-cellsclock-namesnum-csspi-max-frequencyvoltage-rangespl022,interfacepl022,com-modepl022,rx-level-trigpl022,tx-level-trig#gpio-cellsgpio-controllerdevice_typebus-rangemsi-parentinterrupt-map-maskinterrupt-mapiommu-mapreg-sizereg-spacingamd,per-channel-interruptamd,speed-setamd,serdes-blwcamd,serdes-cdr-rateamd,serdes-pq-skewamd,serdes-tx-ampamd,serdes-dfe-tap-configamd,serdes-dfe-tap-enablemac-addressphy-modecpuenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsl2-cachecache-unifiednext-level-cachecache-levelinterrupt-affinitystdout-path