x8q(qradxa,rock-2arockchip,rk3528 +7Radxa ROCK 2Aaliases=/pinctrl/gpio@ff610000C/pinctrl/gpio@ffaf0000I/pinctrl/gpio@ffb00000O/pinctrl/gpio@ffb10000U/pinctrl/gpio@ffb20000[/soc/i2c@ffa58000`/soc/mmc@ffbf0000e/soc/mmc@ffc30000j/soc/serial@ff9f0000r/soc/ethernet@ffbe0000cpus+cpu-mapcluster0core0|core1|core2|core3|cpu@0arm,cortex-a53cpupscicpu@1arm,cortex-a53cpupscicpu@2arm,cortex-a53cpupscicpu@3arm,cortex-a53cpupscifirmwarescmi arm,scmi-smĉ +protocol@14opp-table-cpuoperating-points-v2opp-1200000000G Y Y @opp-1416000000Tfr HH @opp-1608000000_"  @opp-1800000000kI ԼԼ @opp-2016000000x)  @opp-table-gpuoperating-points-v2-opp-300000000 Y YB@opp-500000000e Y YB@opp-600000000#F Y YB@opp-700000000)' B@opp-800000000/ ~~B@pinctrlrockchip,rk3528-pinctrl' +4 gpio@ff610000rockchip,gpio-banka r s ;GFVb ncgpio@ffaf0000rockchip,gpio-bank  ;IFVb n _gpio@ffb00000rockchip,gpio-bank $ % ;KFVb @ n gpio@ffb10000rockchip,gpio-bank  ;LFVb ` n `gpio@ffb20000rockchip,gpio-bank  ;NFVb n Kpcfg-pull-uppcfg-pull-downpcfg-pull-nonepcfg-pull-none-drv-level-0pcfg-pull-none-drv-level-2pcfg-pull-up-drv-level-2pcfg-pull-none-smtarmclkemmcemmc-bus8Lemmc-clkMemmc-cmdNemmc-strbOethfephyfephym0-led-link>fephym0-led-spd?fspigpuhdmihsmi2c0i2c1i2c1m0-xfer 1i2c2i2c2m1-xfer 3i2c3i2c4i2c4-xfer 4i2c5i2c6i2c7i2c7-xfer 5i2s0i2s1jtagpciepdmpmupwm0pwm1pwm1m0-pins6pwm2pwm2m0-pins7pwm3pwm4pwm5pwm6pwm7pwrrefrgmiirgmii-miim Ergmii-rx-bus20Grgmii-tx-bus20Frgmii-rgmii-clk Hrgmii-rgmii-bus@ Iscrsdio0sdio0-bus4@Psdio0-clkQsdio0-cmdRsdio1sdio1-bus4@ Ssdio1-clkTsdio1-cmdUsdmmcsdmmc-bus4@Vsdmmc-clkWsdmmc-cmdXsdmmc-detYsdmmc-vol-ctrl-hespdifspi0spi1tsi0tsi1uart0uart0m0-xfer 0uart1uart2uart3uart4uart5uart6uart7bluetoothbt-wake-host-hhost-wake-bt-hledsstate-led-b]sys-led-g^usbusb-host-endusb-otg-eniwifiusb-wifi-pwrbwifi-reg-on-hhwifi-wake-host-hethernetgmac1-rstn-lJpsciarm,psci-1.0arm,psci-0.2smcreserved-memory+4shmem@10f000arm,scmi-shmem timerarm,armv8-timer0;   clock-xin24m fixed-clockn6xin24mclock-gmac50m fixed-clockgmac0soc simple-bus4+interrupt-controller@fed01000 arm,gic-400@ @ `  ; nqos@ff200000rockchip,rk3528-qossyscon qos@ff200080rockchip,rk3528-qossyscon qos@ff200100rockchip,rk3528-qossyscon  qos@ff200200rockchip,rk3528-qossyscon  qos@ff200280rockchip,rk3528-qossyscon  qos@ff200300rockchip,rk3528-qossyscon  qos@ff200380rockchip,rk3528-qossyscon  qos@ff210000rockchip,rk3528-qossyscon! qos@ff210080rockchip,rk3528-qossyscon! qos@ff220000rockchip,rk3528-qossyscon" qos@ff220080rockchip,rk3528-qossyscon" qos@ff240000rockchip,rk3528-qossyscon$ qos@ff250000rockchip,rk3528-qossyscon% qos@ff260000rockchip,rk3528-qossyscon& qos@ff270000rockchip,rk3528-qossyscon' qos@ff270080rockchip,rk3528-qossyscon' qos@ff270100rockchip,rk3528-qossyscon' qos@ff270200rockchip,rk3528-qossyscon' qos@ff270280rockchip,rk3528-qossyscon' qos@ff270300rockchip,rk3528-qossyscon'  qos@ff270380rockchip,rk3528-qossyscon' !qos@ff270480rockchip,rk3528-qossyscon' "qos@ff270500rockchip,rk3528-qossyscon' #qos@ff280000rockchip,rk3528-qossyscon( $qos@ff280080rockchip,rk3528-qossyscon( %qos@ff280100rockchip,rk3528-qossyscon( &qos@ff280180rockchip,rk3528-qossyscon( 'qos@ff280200rockchip,rk3528-qossyscon( (qos@ff280280rockchip,rk3528-qossyscon( )qos@ff280300rockchip,rk3528-qossyscon( *qos@ff280380rockchip,rk3528-qossyscon( +qos@ff280400rockchip,rk3528-qossyscon( ,syscon@ff340000rockchip,rk3528-vpu-grfsyscon4@syscon@ff348000$rockchip,rk3528-pipe-phy-grfsyscon4[syscon@ff360000rockchip,rk3528-vo-grfsyscon6:clock-controller@ff4a0000rockchip,rk3528-cruJ' t          z y  LL7Fq;;]Q沀eр Cׄ#FsY@e Lxin24mgmac0X syscon@ff540000rockchip,rk3528-ioc-grfsysconT power-management@ff600000&rockchip,rk3528-pmusysconsimple-mfd` power-controller!rockchip,rk3528-power-controllere+ power-domain@4 yepower-domain@5ye disabledpower-domain@6yepower-domain@7$y !"#epower-domain@8$y$%&'()*+,egpu@ff700000"rockchip,rk3528-maliarm,mali-450p' 7@  LbuscoreT;XYV\]Z["gpgpmmupppp0ppmmu0pp1ppmmu1-  wokay.spi@ff9c0000(rockchip,rk3528-spirockchip,rk3066-spi Lspiclkapb_pclk ;//txrx + disabledspi@ff9d0000(rockchip,rk3528-spirockchip,rk3066-spi Lspiclkapb_pclk ;//txrx + disabledserial@ff9f0000&rockchip,rk3528-uartsnps,dw-apb-uart  kLbaudclkapb_pclk ;(/ /okaydefault0serial@ff9f8000&rockchip,rk3528-uartsnps,dw-apb-uart  Lbaudclkapb_pclk ;)/ /   disabledserial@ffa00000&rockchip,rk3528-uartsnps,dw-apb-uart  Lbaudclkapb_pclk ;*/ /   disabledserial@ffa08000&rockchip,rk3528-uartsnps,dw-apb-uart  Lbaudclkapb_pclk ;+//  disabledserial@ffa10000&rockchip,rk3528-uartsnps,dw-apb-uart  1Lbaudclkapb_pclk ;,//  disabledserial@ffa18000&rockchip,rk3528-uartsnps,dw-apb-uart " Lbaudclkapb_pclk ;-//  disabledserial@ffa20000&rockchip,rk3528-uartsnps,dw-apb-uart % Lbaudclkapb_pclk ;.//  disabledserial@ffa28000&rockchip,rk3528-uartsnps,dw-apb-uart ( Lbaudclkapb_pclk ;///  disabledi2c@ffa50000(rockchip,rk3528-i2crockchip,rk3399-i2c  Li2cpclk ;= + disabledi2c@ffa58000(rockchip,rk3528-i2crockchip,rk3399-i2c  Li2cpclk ;> +okaydefault1eeprom@50belling,bl24c16aatmel,24c16P2i2c@ffa60000(rockchip,rk3528-i2crockchip,rk3399-i2c j i Li2cpclk ;?default3+ disabledi2c@ffa68000(rockchip,rk3528-i2crockchip,rk3399-i2c  Li2cpclk ;@ + disabledi2c@ffa70000(rockchip,rk3528-i2crockchip,rk3399-i2c 3 2 Li2cpclk ;Adefault4 + disabledi2c@ffa78000(rockchip,rk3528-i2crockchip,rk3399-i2c  Li2cpclk ;B + disabledi2c@ffa80000(rockchip,rk3528-i2crockchip,rk3399-i2c  Li2cpclk ;C + disabledi2c@ffa88000(rockchip,rk3528-i2crockchip,rk3399-i2c 5 4 Li2cpclk ;Ddefault5 + disabledpwm@ffa90000(rockchip,rk3528-pwmrockchip,rk3328-pwm o n Lpwmpclk disabledpwm@ffa90010(rockchip,rk3528-pwmrockchip,rk3328-pwm o n Lpwmpclkokaydefault6fpwm@ffa90020(rockchip,rk3528-pwmrockchip,rk3328-pwm  o n Lpwmpclkokaydefault7gpwm@ffa90030(rockchip,rk3528-pwmrockchip,rk3328-pwm0 o n Lpwmpclk disabledpwm@ffa98000(rockchip,rk3528-pwmrockchip,rk3328-pwm r q Lpwmpclk disabledpwm@ffa98010(rockchip,rk3528-pwmrockchip,rk3328-pwm r q Lpwmpclk disabledpwm@ffa98020(rockchip,rk3528-pwmrockchip,rk3328-pwm  r q Lpwmpclk disabledpwm@ffa98030(rockchip,rk3528-pwmrockchip,rk3328-pwm0 r q Lpwmpclk disabledadc@ffae0000rockchip,rk3528-saradc Lsaradcapb_pclk ;  o saradc-apbokay/8\ethernet@ffbd0000&rockchip,rk3528-gmacsnps,dwmac-4.20a0      >Lstmmacethclk_mac_refmac_clk_rxmac_clk_txpclk_macaclk_mac;qtmacirqeth_wake_irq;9Frmii   stmmaceth':O;_p<= disabledmdiosnps,dwmac-mdio+ethernet-phy@2ethernet-phy-ieee802.3-c22 "default>? 9stmmac-axi-config;rx-queues-config<queue0tx-queues-config=queue0ethernet@ffbe0000&rockchip,rk3528-gmacsnps,dwmac-4.20a (Lstmmacethclk_mac_refpclk_macaclk_mac;y|macirqeth_wake_irq  a stmmaceth'@OA_pBCokayoutput;D Frgmii-id2defaultEFGHImdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22defaultJN / AKDstmmac-axi-configArx-queues-configBqueue0tx-queues-configCqueue0mmc@ffbf00000rockchip,rk3528-dwcmshcrockchip,rk3588-dwcmshc'  7 n6 ( Lcorebusaxiblocktimer ;M defaultLMNO ( A B C D Ecorebusaxiblocktimerokay[ew28mmc@ffc100000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@  Lbiuciuciu-driveciu-sample ;M default PQR  greset disabledmmc@ffc200000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@  Lbiuciuciu-driveciu-sample ;M default STU  hreset disabledmmc@ffc300000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@ ( '  Lbiuciuciu-driveciu-sample ;MdefaultVWXY  resetZokay[e2Zdma-controller@ffd60000arm,pl330arm,primecell@ ^ Lapb_pclkl;/phy@ffdc0000rockchip,rk3528-naneng-combphy' {7 {  Lrefapbpipe  c ephyapb0;@M[ disabledchosencserial0:1500000n8adc-keys adc-keyso\{buttonsw@dbutton-maskromMASKROMleds gpio-ledsdefault]^led-0on heartbeat G_ heartbeatled-1onstatus G` default-onregulator-0v9-vddregulator-fixedvdd_0v9!5G _ waregulator-1v1-vcc-ddrregulator-fixedvcc_ddr!5G_waregulator-1v8-vccregulator-fixedvcc_1v8!5Gw@_w@w28regulator-3v3-vccregulator-fixedvcc_3v3!5G2Z_2Zwa2regulator-3v3-vcc-wifiregulator-fixed GKdefaultb vcc_wifiG2Z_2Zw2regulator-5v0-vcc-sysregulator-fixed vcc5v0_sys!5GLK@_LK@aregulator-5v0-vcc-usb20regulator-fixed Gcdefaultd vcc5v0_usb20GLK@_LK@waregulator-vccio-sdregulator-gpio G_defaulte vccio_sdGw@_2Zw@2ZwaZregulator-vdd-armpwm-regulatorfavdd_arm!5G b_Shregulator-vdd-logicpwm-regulatorga vdd_logic!5G _Y.rfkill rfkill-gpio rfkill-wlandefaulthwlan _regulator-5v0-vcc-usb30-otgregulator-fixed G_defaultivcc5v0_usb30_otgGLK@_LK@wa compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c1mmc0mmc1serial0ethernet0cpuregdevice_typeenable-methodclocksoperating-points-v2cpu-supplyphandlearm,smc-idshmem#clock-cellsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrangesinterruptsgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspower-domainsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsno-mapclock-frequencyclock-output-namesassigned-clocksassigned-clock-ratesclock-names#reset-cells#power-domain-cellspm_qosstatusinterrupt-namesresetsmali-supplydmasdma-namesreg-io-widthreg-shiftpinctrl-namespinctrl-0pagesizeread-onlyvcc-supply#pwm-cellsreset-names#io-channel-cellsvref-supplyphy-handlephy-modesnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-is-integratedsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useclock_in_outphy-supplyreset-assert-usreset-deassert-usreset-gpiosmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vno-sdno-sdionon-removablevmmc-supplyvqmmc-supplyfifo-depthrockchip,default-sample-phasecap-sd-highspeeddisable-wpsd-uhs-sdr104#dma-cellsarm,pl330-periph-burst#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statefunctionlinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highstatespwmspwm-supplyregulator-settling-time-up-usradio-typeshutdown-gpios