8h( 0'friendlyarm,nanopi-r2srockchip,rk3328 +7FriendlyElec NanoPi R2Saliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/usb@ff600000/device@2/mmc@ff500000cpus+cpu@0cpuarm,cortex-a53xpsci @+8E@Wdu cpu@1cpuarm,cortex-a53xpsci @+8E@Wdu cpu@2cpuarm,cortex-a53xpsci @+8E@Wdu cpu@3cpuarm,cortex-a53xpsci @+8E@Wdu idle-statespscicpu-sleeparm,idle-statexl2-cachecache@-opp-table-0operating-points-v2 opp-408000000Q~)@:opp-600000000#F~)@opp-8160000000,B@)@opp-1008000000<)@opp-1200000000G()@opp-1296000000M?d )@analog-soundsimple-audio-cardFi2s_yAnalog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem  disabledhdmi-soundsimple-audio-cardFi2s_yHDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mGi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk tx!default/ disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrx!defaultsleep/9 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfdEio-domains"rockchip,rk3328-io-voltage-domainokayCP^lzgpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+<power-domain@1power-domain@6Dpower-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrx!default / !" disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrx!default /#$% disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrx!default/&okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk!default/' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk!default/(okaypmic@18rockchip,rk805 )xin32krk805-clkout2/*!default(@N+Z+f+r+~+regulatorsDCDC_REG1vdd_log 4 0regulator-state-mem(B@DCDC_REG2vdd_arm 4 0regulator-state-mem(~DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4 vcc_io_332Z2Zregulator-state-mem(2ZLDO_REG1vcc_18w@w@regulator-state-mem(w@LDO_REG2 vcc18_emmcw@w@regulator-state-mem(w@LDO_REG3vdd_10B@B@regulator-state-mem(B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk!default/, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk!default/- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrx!default/./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk!default/2D disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk!default/3D disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclk!default/4Dokaypwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk!default/5D disableddma-controller@ff1f0000arm,pl330arm,primecell@O apb_pclkfthermal-zonessoc-thermalq6tripstrip-point0ppassivetrip-point1Lpassive7soc-crits criticalcooling-mapsmap070 map17 8tsadc@ff250000rockchip,rk3328-tsadc% :$P$tsadcapb_pclk!initdefaultsleep/99:9B %tsadc-apb1Hokay^u6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aHadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclkV %saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore;<f8opp-table-gpuoperating-points-v2;opp-200000000 g8opp-300000000g8opp-400000000ׄg8opp-500000000e0 disablediommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk=<iommu@ff350800rockchip,iommu5@  F aclkiface<=video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreAB ׄׄ><iommu@ff360480rockchip,iommu 6@6@ JB aclkiface<>vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop %axiahbdclk? disabledport endpoint@Fiommu@ff373f00rockchip,iommu7?  ; aclkiface disabled?hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #FiahbisfrcecAhdmi!default /BCD E disabledports+port@0endpointF@port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk E disabledphy@ff430000rockchip,rk3328-hdmi-phyC SGysysclkrefoclkrefpclk hdmi_phyH %cpu-version6 disabledAclock-controller@ff440000rockchip,rk3328-cruDGxin24m EAx=&'(ABDC"\5H4$NzGGG|n6n6n6ׄn6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyGphyclk usb480m_phy{NIokayIotg-port6$;<=otg-bvalidotg-idlinestateokayVhost-port6 > linestateokayWmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleepрm%resetokay~/JKLM!defaultNmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleepрn%reset disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleepрo%reset disabledethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc %stmmaceth EokaydfNOOinput&rgmii//P!default:QE$Nmdiosnps,dwmac-mdio+ethernet-phy@1/R!defaultW'gP y)Qethernet@ff550000rockchip,rk3328-gmacU E macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb %stmmaceth&rmii:Soutput disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22Vd!default/TUSusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost@ V usb2-phyokayusb@ff5c0000 generic-ehci\  NIWusbokayusb@ff5d0000 generic-ohci]  NIWusbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-sampleepрh%reset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkhost utmi_wide  3 T mokay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400  @ @ `   crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclkD %crypto-rstpinctrlrockchip,rk3328-pinctrl E+ gpio@ff210000rockchip,gpio-bank! 3  dgpio@ff220000rockchip,gpio-bank" 4  )gpio@ff230000rockchip,gpio-bank# 5  hgpio@ff240000rockchip,gpio-bank$ 6  pcfg-pull-up Zpcfg-pull-down bpcfg-pull-none Xpcfg-pull-none-2ma  apcfg-pull-up-2ma  pcfg-pull-up-4ma  [pcfg-pull-none-4ma  ^pcfg-pull-down-4ma  pcfg-pull-none-8ma  \pcfg-pull-up-8ma  ]pcfg-pull-none-12ma  _pcfg-pull-up-12ma  `pcfg-output-high pcfg-output-low pcfg-input-high  Ypcfg-input i2c0i2c0-xfer XX'i2c1i2c1-xfer XX(i2c2i2c2-xfer  XX,i2c3i2c3-xfer XX-i2c3-pins XXhdmi_i2chdmii2c-xfer XXCpdm-0pdmm0-clk Xpdmm0-fsync Xpdmm0-sdi0 Xpdmm0-sdi1 Xpdmm0-sdi2 Xpdmm0-sdi3 Xpdmm0-clk-sleep Ypdmm0-sdi0-sleep Ypdmm0-sdi1-sleep Ypdmm0-sdi2-sleep Ypdmm0-sdi3-sleep Ypdmm0-fsync-sleep Ytsadcotp-pin  X9otp-out  X:uart0uart0-xfer  XZ uart0-cts  X!uart0-rts  X"uart0-rts-pin  Xuart1uart1-xfer XZ#uart1-cts X$uart1-rts X%uart1-rts-pin Xuart2-0uart2m0-xfer XZuart2-1uart2m1-xfer XZ&spi0-0spi0m0-clk Zspi0m0-cs0  Zspi0m0-tx  Zspi0m0-rx  Zspi0m0-cs1  Zspi0-1spi0m1-clk Zspi0m1-cs0 Zspi0m1-tx Zspi0m1-rx Zspi0m1-cs1 Zspi0-2spi0m2-clk Z.spi0m2-cs0 Z1spi0m2-tx Z/spi0m2-rx Z0i2s1i2s1-mclk Xi2s1-sclk Xi2s1-lrckrx Xi2s1-lrcktx Xi2s1-sdi Xi2s1-sdo Xi2s1-sdio1 Xi2s1-sdio2 Xi2s1-sdio3 Xi2s1-sleep YYYYYYYYYi2s2-0i2s2m0-mclk Xi2s2m0-sclk Xi2s2m0-lrckrx Xi2s2m0-lrcktx Xi2s2m0-sdi Xi2s2m0-sdo Xi2s2m0-sleep` YYYYYYi2s2-1i2s2m1-mclk Xi2s2m1-sclk Xi2sm1-lrckrx Xi2s2m1-lrcktx Xi2s2m1-sdi Xi2s2m1-sdo Xi2s2m1-sleepP YYYYYspdif-0spdifm0-tx Xspdif-1spdifm1-tx Xspdif-2spdifm2-tx Xsdmmc0-0sdmmc0m0-pwren [sdmmc0m0-pin [sdmmc0-1sdmmc0m1-pwren [sdmmc0m1-pin [jsdmmc0sdmmc0-clk \Jsdmmc0-cmd ]Ksdmmc0-dectn [Lsdmmc0-wrprt [sdmmc0-bus1 ]sdmmc0-bus4@ ]]]]Msdmmc0-pins [[[[[[[[sdmmc0extsdmmc0ext-clk ^sdmmc0ext-cmd [sdmmc0ext-wrprt [sdmmc0ext-dectn [sdmmc0ext-bus1 [sdmmc0ext-bus4@ [[[[sdmmc0ext-pins [[[[[[[[sdmmc1sdmmc1-clk  \sdmmc1-cmd  ]sdmmc1-pwren ]sdmmc1-wrprt ]sdmmc1-dectn ]sdmmc1-bus1 ]sdmmc1-bus4@ ]]]]sdmmc1-pins  [ [[[[[[[[emmcemmc-clk _emmc-cmd `emmc-pwren Xemmc-rstnout Xemmc-bus1 `emmc-bus4@ ````emmc-bus8 ````````pwm0pwm0-pin X2pwm1pwm1-pin X3pwm2pwm2-pin X4pwmirpwmir-pin X5gmac-1rgmiim1-pins`  \ ^^\^^^ ^ ^\ \^^\\\ \^\\\\Prmiim1-pins a_aaaa a a_ _ X XXXXXgmac2phyfephyled-speed10 Xfephyled-duplex Xfephyled-rxm1 XTfephyled-txm1 Xfephyled-linkm1 XUtsadc_pintsadc-int  Xtsadc-pin  Xhdmi_pinhdmi-cec XBhdmi-hpd bDcif-0dvp-d2d9-m0 XXXXX X X XXXXXcif-1dvp-d2d9-m1 XXXXXXXXXXXXbuttonreset-button-pin Xcgmac2ioeth-phy-reset-pin bRledslan-led-pin Xesys-led-pin Xfwan-led-pin Xglanlan-vdd-pin Xkpmicpmic-int-l Z*sdsdio-vcc-pin Zichosen serial2:1500000n8gmac-clock fixed-clocksY@ gmac_clkinOkeys gpio-keys/c!defaultkey-reset )reset d / :2leds gpio-leds /efg!defaultled-0 h )nanopi-r2s:green:lanled-1 d )nanopi-r2s:red:sys Lonled-2 h )nanopi-r2s:green:wanregulator-sdmmcioregulator-gpio Z )/i!default vcc_io_sdiow@2Z m voltage w@2Z regulator-sdmmcregulator-fixed d/j!defaultvcc_sd2Z2Z Nregulator-vdd-5vregulator-fixedvdd_5vLK@LK@+regulator-vdd-5v-lanregulator-fixed Z h/k!default vdd_5v_lan + compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domains#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplytx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-modephy-supplyphy-handletx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio